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g2384 / VHDLFormatter

VHDL formatter web online written in typescript
https://g2384.github.io/VHDLFormatter/
MIT License
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std_logic and vector type is not formatted #33

Closed NINI1988 closed 4 years ago

NINI1988 commented 4 years ago

Report a bug

std_logic and std_logic_vector are not formatted to uppercase, but integer does. Is this behavior wanted?

Type name case: UPPERCASE

Input

ENTITY TriggerTime IS

  PORT (
    a: OUT std_logic;
    b: IN std_logic_vector(1 DOWNTO 0);
    c: IN integer
  );

Expected Behavior

ENTITY TriggerTime IS

    PORT (
        a : OUT STD_LOGIC;
        b : IN STD_LOGIC_VECTOR(1 DOWNTO 0);
        c : IN INTEGER

    );

Actual Behavior

ENTITY TriggerTime IS

    PORT (
        a : OUT std_logic;
        b : IN std_logic_vector(1 DOWNTO 0);
        c : IN INTEGER

    );
g2384 commented 4 years ago

this has been fixed. Thanks for the feedback.