Problem with the "Align signs in all places" option

[grigosback]

Request a new feature

When declaring constants and having the "align all" option set to "true", the alignment may separate the constant name far from the set value for that constant. The same happens in the declaration of signals. Is it possible to separate the alignment group of constants and signals by types?

Example Input:

constant SC_DATA_WIDTH : integer := 8;
constant SCR_NORMAL_BYTE_COUNT : integer := 511;
constant SCR_SHORT_BYTE_COUNT : integer := 1;
constant SCR_NORMAL_BIT_COUNT : integer := 7;
constant SCR_SHORT_BIT_COUNT : integer := 2;
constant TX_FIFO_DATA_WIDTH : integer := SC_DATA_WIDTH;
constant TX_FIFO_ADDR_WIDTH : integer := 7;
constant RX_FIFO_DATA_WIDTH : integer := SC_DATA_WIDTH;
constant RX_FIFO_ADDR_WIDTH : integer := 7;
constant NULL_CHARACTER : std_logic_vector(SC_DATA_WIDTH - 1 downto 0) := (others => '0');

signal user_start_write, user_start_read, user_fin_read, user_fin_write, user_read_mismatch, byte_high, command : std_logic;
signal user_addr, user_wdata, user_rdata, user_rxdata, slv_addr : std_logic_vector(31 downto 0);
signal command_code : std_logic_vector(3 downto 0);

Example Output:

constant SC_DATA_WIDTH         : integer := 8;
constant SCR_NORMAL_BYTE_COUNT : integer := 511;
constant SCR_SHORT_BYTE_COUNT  : integer := 1;
constant SCR_NORMAL_BIT_COUNT  : integer := 7;
constant SCR_SHORT_BIT_COUNT   : integer := 2;
constant TX_FIFO_DATA_WIDTH    : integer := SC_DATA_WIDTH;
constant TX_FIFO_ADDR_WIDTH    : integer := 7;
constant RX_FIFO_DATA_WIDTH    : integer := SC_DATA_WIDTH;
constant RX_FIFO_ADDR_WIDTH    : integer := 7;
constant NULL_CHARACTER : std_logic_vector(SC_DATA_WIDTH - 1 downto 0) := (others => '0');

signal user_start_write, user_start_read, user_fin_read, user_fin_write, user_read_mismatch, byte_high, command : std_logic;
signal user_addr, user_wdata, user_rdata, user_rxdata, slv_addr : std_logic_vector(31 downto 0);
signal command_code : std_logic_vector(3 downto 0);
signal vector       : std_logic_vector(3 downto 0);

Actual Behavior

constant SC_DATA_WIDTH         : integer                                      := 8;
constant SCR_NORMAL_BYTE_COUNT : integer                                      := 511;
constant SCR_SHORT_BYTE_COUNT  : integer                                      := 1;
constant SCR_NORMAL_BIT_COUNT  : integer                                      := 7;
constant SCR_SHORT_BIT_COUNT   : integer                                      := 2;
constant TX_FIFO_DATA_WIDTH    : integer                                      := SC_DATA_WIDTH;
constant TX_FIFO_ADDR_WIDTH    : integer                                      := 7;
constant RX_FIFO_DATA_WIDTH    : integer                                      := SC_DATA_WIDTH;
constant RX_FIFO_ADDR_WIDTH    : integer                                      := 7;
constant NULL_CHARACTER        : std_logic_vector(SC_DATA_WIDTH - 1 downto 0) := (others => '0');

signal user_start_write, user_start_read, user_fin_read, user_fin_write, user_read_mismatch, byte_high, command : std_logic;
signal user_addr, user_wdata, user_rdata, user_rxdata, slv_addr                                                 : std_logic_vector(31 downto 0);
signal command_code                                                                                             : std_logic_vector(3 downto 0);
signal vector                                                                                                   : std_logic_vector(3 downto 0);

[g2384]

This seems a very clever solution. I'll see if it can be improved.