g2384 / VHDLFormatter

VHDL formatter web online written in typescript
https://g2384.github.io/VHDLFormatter/
MIT License
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The label for the process is not indented/aligned properly #4

Closed goglecm closed 6 years ago

goglecm commented 6 years ago

I've noticed an issue with the indentation/alignment. When a label is used for a process, the whole line gets misaligned if there are "long" variable declarations that follow. Here is an example (original code) of how the "label : process" statement should look like.

architecture behaviour of A_ARITH_MOD is
begin
    main : process -- (PROBLEM IS HERE!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!)
        variable tempResult            : data_qword  := (others => DR_INIT);
        variable minSize, requiredSize : positive     := 8;
        variable totalResults          : natural      := 0;
        -- Local registers
        variable localStatusRegister   : data_bit_vector((S_ALU_STATUS - 1) downto 0) := (others => DR_ZERO);
    begin

    end process main;

end architecture behaviour;

and here is how it gets formatted.

architecture behaviour of A_ARITH_MOD is
begin
    main                           : process -- (PROBLEM IS HERE!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!!)
        variable tempResult            : data_qword                                   := (others => DR_INIT);
        variable minSize, requiredSize : positive                                     := 8;
        variable totalResults          : natural                                      := 0;
        -- Local registers
        variable localStatusRegister   : data_bit_vector((S_ALU_STATUS - 1) downto 0) := (others => DR_ZERO);
    begin

    end process main;

end architecture behaviour;

as you can see the distance between the label "main" and the keyword "process is huge". Some users put the keyword "process" in a new line after the label. No issues there. Here is an example (formatted code).

architecture behaviour of A_ARITH_MOD is
begin
    main :
    process -- (No problems here)
        variable tempResult            : data_qword                                   := (others => DR_INIT);
        variable minSize, requiredSize : positive                                     := 8;
        variable totalResults          : natural                                      := 0;
        -- Local registers
        variable localStatusRegister   : data_bit_vector((S_ALU_STATUS - 1) downto 0) := (others => DR_ZERO);
    begin

    end process main;

end architecture behaviour;
g2384 commented 6 years ago

fixed