incorrect indentation on consecutive component instantiations

[ed-boon]

incorrect indentation on consecutive component instantiations

Note: the problem does not occur if the component and port map keywords are in the same line of code.

Input

test_iobuf : component IOBUF
port map(
    I  => '0',
    IO => open,
    O  => open,
    T  => '0'
);
test_iobuf2 : component IOBUF
port map(
    I  => '0',
    IO => open,
    O  => open,
    T  => '0'
);
test_iobuf3 : component IOBUF
port map(
    I  => '0',
    IO => open,
    O  => open,
    T  => '0'
);

Expected Behavior

        test_iobuf : component IOBUF
            port map(
                I  => '0',
                IO => open,
                O  => open,
                T  => '0'
            );

        test_iobuf2 : component IOBUF
            port map(
                I  => '0',
                IO => open,
                O  => open,
                T  => '0'
            );

        test_iobuf3 : component IOBUF
            port map(
                I  => '0',
                IO => open,
                O  => open,
                T  => '0'
            );

Actual Behavior

test_iobuf : component IOBUF
            port map(
                I  => '0',
                IO => open,
                O  => open,
                T  => '0'
            );
            test_iobuf2 : component IOBUF
                port map(
                    I  => '0',
                    IO => open,
                    O  => open,
                    T  => '0'
                );
                test_iobuf3 : component IOBUF
                    port map(
                        I  => '0',
                        IO => open,
                        O  => open,
                        T  => '0'
                    );

[g2384]

Thanks for this bug report. I believe this has been fixed now.

[ed-boon]

Thank you so much for working on it!

The Formatter still seems to have the same problem when the component instantiations have a generic map. This one:

test_buf : component buf
generic map(
test => '0',
test2 => '1'
)
port map(
    I  => '0',
    IO => open,
    O  => open,
    T  => '0'
);

test_buf : component buf
generic map(
test => '0',
test2 => '1'
)
port map(
    I  => '0',
    IO => open,
    O  => open,
    T  => '0'
);

test_buf : component buf
generic map(
test => '0',
test2 => '1'
)
port map(
    I  => '0',
    IO => open,
    O  => open,
    T  => '0'
);

still lines up like that

test_buf : component buf
        generic map(
            test => '0',
            test2 => '1'
        )
        port map(
            I => '0',
            IO => open,
            O => open,
            T => '0'
        );

        test_buf : component buf
            generic map(
                test => '0',
                test2 => '1'
            )
            port map(
                I => '0',
                IO => open,
                O => open,
                T => '0'
            );

            test_buf : component buf
                generic map(
                    test => '0',
                    test2 => '1'
                )
                port map(
                    I => '0',
                    IO => open,
                    O => open,
                    T => '0'
                );

Best regards