Formal Verification/PSL operators get split up

[timkruse]

Report a bug

vhdl2008 implements formal verification (psl) syntax within the vhdl source code and introduces some new operators. For this issue the |=> and |-> operators are of interest. After formatting the bar | splits apart from the operator and hence doesn't compile anymore.

Input

assert always {reset} |=> {not o_valid};
assert always {s_data(0) /= s_data(1)} |-> {o_valid};

Expected Behavior

assert always {reset} |=> {not o_valid};
assert always {s_data(0) /= s_data(1)} |-> {o_valid};

Actual Behavior

assert always {reset} | => {not o_valid}; 
assert always {s_data(0) /= s_data(1)} | -> {o_valid};

Mind the spaces after the bars.