Spaces in port declerations

[efeyitim]

I think std_logic_vectors should be aligned when there are both in and out ports. Also, aligning downto keyword would be better IMO.

Report a bug

Input

-- sample code here

Expected Behavior

entity my_module is
    port (
        clk : in std_logic;
        rst : in std_logic;
        signal1 : in std_logic_vector(7 downto 0);
        signal2 : in std_logic_vector(31 downto 0);
        signal3 : out std_logic_vector(7 downto 0);
        signal4 : out std_logic_vector(31 downto 0);
    );
end my_module;

Actual Behavior

entity my_module is
    port (
        clk     : in std_logic;
        rst     : in std_logic;
        signal1 : in std_logic_vector(7 downto 0);
        signal2 : in std_logic_vector(31 downto 0);
        signal3 : out std_logic_vector(7 downto 0);
        signal4 : out std_logic_vector(31 downto 0);
    );
end my_module;

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Request a new feature

As a user, I want to...

Example Input:

-- sample code here

Example Output:

entity my_module is
    port (
        clk     : in  std_logic;
        rst     : in  std_logic;
        signal1 : in  std_logic_vector(7  downto 0);
        signal2 : in  std_logic_vector(31 downto 0);
        signal3 : out std_logic_vector(7  downto 0);
        signal4 : out std_logic_vector(31 downto 0);
    );
end my_module;