Open Sp1ffyG33k opened 2 years ago
When same components are instantiated back-to-back, each instantiated component gets indented one extra space. Simplified sample code below. Please observe second component instance when formatted. It moved one additional space in.
This behavior is replicated both on vscode and https://g2384.github.io/VHDLFormatter/
--================================================================================================== -- Library Definitions --================================================================================================== LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; USE IEEE.math_real.ALL; -- needed for CEIL and LOG functions LIBRARY work; --================================================================================================== -- Entity Definition --================================================================================================== ENTITY someModule IS PORT ( mdmClk : IN std_logic; mdmClkRst_n : IN std_logic; intf_rdy : IN STD_LOGIC ); END someModule; --================================================================================================== -- Architecture --================================================================================================== ARCHITECTURE rtl OF someModule IS ---------------------------------------------------------------------------------------------------- -- Component Declarations ---------------------------------------------------------------------------------------------------- COMPONENT genericCSR GENERIC( -- SomeWidth : positive := SomeWidth; --Defined in gernericCSR_pkg (see Known Issues above) EnableBit : std_logic_vector(SomeWidth-1 DOWNTO 0) := (OTHERS => '1'); ResetValue : std_logic_vector(SomeWidth-1 DOWNTO 0) := (OTHERS => '0'); PassThru : std_logic_vector(SomeWidth-1 DOWNTO 0) := (OTHERS => '0'); ReadOnly : std_logic_vector(SomeWidth-1 DOWNTO 0) := (OTHERS => '0'); SelfClr : std_logic_vector(SomeWidth-1 DOWNTO 0) := (OTHERS => '0'); Write1ToClr : std_logic_vector(SomeWidth-1 DOWNTO 0) := (OTHERS => '0'); ReadToClr : std_logic_vector(SomeWidth-1 DOWNTO 0) := (OTHERS => '0'); SignExtend : boolean := FALSE; AppHasPriority : boolean := TRUE; NumCntrs : natural := 0; --when non-zero, must match number of msb/lsb pairs CntrDefArray : cntrDefArray_type := (2 => (msb => 31, lsb => 16), --descending range! 1 => (msb => 15, lsb => 8), --do not overlap bits 0 => (msb => 7, lsb => 0)) --msb must be >= lsb ); PORT( --note default values are used so an instantiation can omit unassigned input ports clk : IN std_logic := '0'; rst_n : IN std_logic := '0'; mpWr : IN std_logic := '0'; mpRd : IN std_logic := '0'; mpSel : IN std_logic := '0'; --mp address decode mpWrData : IN std_logic_vector(SomeWidth - 1 DOWNTO 0) := (OTHERS => '0'); mpBE : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '1'); appWrBit : IN std_logic_vector(SomeWidth - 1 DOWNTO 0) := (OTHERS => '0'); appWrData : IN std_logic_vector(SomeWidth - 1 DOWNTO 0) := (OTHERS => '0'); appIncr : IN std_logic_vector(NumCntrs DOWNTO 0) := (OTHERS => '0'); csr_q : OUT std_logic_vector(SomeWidth - 1 DOWNTO 0) ); END COMPONENT genericCSR; --================================================================================================== -- Behavioral Description --================================================================================================== BEGIN u_mdmStatusReg00: COMPONENT genericCSR GENERIC MAP ( -- Write1ToClr => X"0000FFFF", EnableBit => X"FFFFFFFF", PassThru => X"FFFF_FFFF", ReadOnly => X"FFFF_FFFF", ResetValue => X"00000000" ) PORT MAP ( clk => mdmClk, rst_n => mdmClkRst_n, mpSel => csrSelect(ADDR_SomeStatusReg00), mpWr => mci_cscWpulse_rq, mpWrData => mci_cscWdata_rq, mpRd => mci_cscRpulse_rq, appWrData => version_number, csr_q => csrArray_rq(ADDR_SomeStatusReg00) ); version_number <= x"A1B2C3D4"; -- repeat the components to reproduce the bug u_mdmStatusReg00: COMPONENT genericCSR GENERIC MAP ( -- Write1ToClr => X"0000FFFF", EnableBit => X"FFFFFFFF", PassThru => X"FFFF_FFFF", ReadOnly => X"FFFF_FFFF", ResetValue => X"00000000" ) PORT MAP ( clk => mdmClk, rst_n => mdmClkRst_n, mpSel => csrSelect(ADDR_SomeStatusReg00), mpWr => mci_cscWpulse_rq, mpWrData => mci_cscWdata_rq, mpRd => mci_cscRpulse_rq, appWrData => version_number, csr_q => csrArray_rq(ADDR_SomeStatusReg00) ); ---------------------------------------------------------------------------------------------------- -- Module End ---------------------------------------------------------------------------------------------------- END rtl;
Formatting should not get indented additionally at the end of each component.
-- sample code here
--================================================================================================== -- Library Definitions --================================================================================================== LIBRARY ieee; USE ieee.std_logic_1164.ALL; USE ieee.numeric_std.ALL; USE IEEE.math_real.ALL; -- needed for CEIL and LOG functions LIBRARY work; --================================================================================================== -- Entity Definition --================================================================================================== ENTITY someModule IS PORT ( mdmClk : IN std_logic; mdmClkRst_n : IN std_logic; intf_rdy : IN std_logic ); END someModule; --================================================================================================== -- Architecture --================================================================================================== ARCHITECTURE rtl OF someModule IS ---------------------------------------------------------------------------------------------------- -- Component Declarations ---------------------------------------------------------------------------------------------------- COMPONENT genericCSR GENERIC ( -- SomeWidth : positive := SomeWidth; --Defined in gernericCSR_pkg (see Known Issues above) EnableBit : std_logic_vector(SomeWidth - 1 DOWNTO 0) := (OTHERS => '1'); ResetValue : std_logic_vector(SomeWidth - 1 DOWNTO 0) := (OTHERS => '0'); PassThru : std_logic_vector(SomeWidth - 1 DOWNTO 0) := (OTHERS => '0'); ReadOnly : std_logic_vector(SomeWidth - 1 DOWNTO 0) := (OTHERS => '0'); SelfClr : std_logic_vector(SomeWidth - 1 DOWNTO 0) := (OTHERS => '0'); Write1ToClr : std_logic_vector(SomeWidth - 1 DOWNTO 0) := (OTHERS => '0'); ReadToClr : std_logic_vector(SomeWidth - 1 DOWNTO 0) := (OTHERS => '0'); SignExtend : boolean := FALSE; AppHasPriority : boolean := TRUE; NumCntrs : natural := 0; --when non-zero, must match number of msb/lsb pairs CntrDefArray : cntrDefArray_type := (2 => (msb => 31, lsb => 16), --descending range! 1 => (msb => 15, lsb => 8), --do not overlap bits 0 => (msb => 7, lsb => 0)) --msb must be >= lsb ); PORT ( --note default values are used so an instantiation can omit unassigned input ports clk : IN std_logic := '0'; rst_n : IN std_logic := '0'; mpWr : IN std_logic := '0'; mpRd : IN std_logic := '0'; mpSel : IN std_logic := '0'; --mp address decode mpWrData : IN std_logic_vector(SomeWidth - 1 DOWNTO 0) := (OTHERS => '0'); mpBE : IN std_logic_vector(3 DOWNTO 0) := (OTHERS => '1'); appWrBit : IN std_logic_vector(SomeWidth - 1 DOWNTO 0) := (OTHERS => '0'); appWrData : IN std_logic_vector(SomeWidth - 1 DOWNTO 0) := (OTHERS => '0'); appIncr : IN std_logic_vector(NumCntrs DOWNTO 0) := (OTHERS => '0'); csr_q : OUT std_logic_vector(SomeWidth - 1 DOWNTO 0) ); END COMPONENT genericCSR; --================================================================================================== -- Behavioral Description --================================================================================================== BEGIN u_mdmStatusReg00 : COMPONENT genericCSR GENERIC MAP( -- Write1ToClr => X"0000FFFF", EnableBit => X"FFFFFFFF", PassThru => X"FFFF_FFFF", ReadOnly => X"FFFF_FFFF", ResetValue => X"00000000" ) PORT MAP( clk => mdmClk, rst_n => mdmClkRst_n, mpSel => csrSelect(ADDR_SomeStatusReg00), mpWr => mci_cscWpulse_rq, mpWrData => mci_cscWdata_rq, mpRd => mci_cscRpulse_rq, appWrData => version_number, csr_q => csrArray_rq(ADDR_SomeStatusReg00) ); version_number <= x"A1B2C3D4"; -- repeat the components to reproduce the bug u_mdmStatusReg00 : COMPONENT genericCSR GENERIC MAP( -- Write1ToClr => X"0000FFFF", EnableBit => X"FFFFFFFF", PassThru => X"FFFF_FFFF", ReadOnly => X"FFFF_FFFF", ResetValue => X"00000000" ) PORT MAP( clk => mdmClk, rst_n => mdmClkRst_n, mpSel => csrSelect(ADDR_SomeStatusReg00), mpWr => mci_cscWpulse_rq, mpWrData => mci_cscWdata_rq, mpRd => mci_cscRpulse_rq, appWrData => version_number, csr_q => csrArray_rq(ADDR_SomeStatusReg00) ); ---------------------------------------------------------------------------------------------------- -- Module End ---------------------------------------------------------------------------------------------------- END rtl;
When same components are instantiated back-to-back, each instantiated component gets indented one extra space. Simplified sample code below. Please observe second component instance when formatted. It moved one additional space in.
This behavior is replicated both on vscode and https://g2384.github.io/VHDLFormatter/
Report a bug
Input
Expected Behavior
Formatting should not get indented additionally at the end of each component.
Actual Behavior