g2384 / VHDLFormatter

VHDL formatter web online written in typescript
https://g2384.github.io/VHDLFormatter/
MIT License
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The spacing in port mapping is not done properly #6

Closed goglecm closed 6 years ago

goglecm commented 6 years ago

Issue 1: When you do port mapping and you put a label for it the space between the label is too long for no apparent reason. Here is the original code.

--
architecture behaviour of A_REG_BANK_MOD is
    -- Components
    component A_REG_MOD
        port
        (
            port_bytes_in           : in data_size_selector
        );
    end component A_REG_MOD;

begin

    main_bank : for i in 0 to S_REG_BANK_SIZE - 1 generate
        reg : A_REG_MOD port -- PROBLEM IS HERE!!!!
        map(
        port_bytes_in   => port_bytes_in(i)
        );
    end generate main_bank;

end architecture behaviour;

This gets formatted to

--
architecture behaviour of A_REG_BANK_MOD is
    -- Components
    component A_REG_MOD
        port
        (
            port_bytes_in : in data_size_selector
        );
    end component A_REG_MOD;

begin

    main_bank : for i in 0 to S_REG_BANK_SIZE - 1 generate
        reg       : A_REG_MOD port -- PROBLEM IS HERE!!!!
        map(
        port_bytes_in => port_bytes_in(i)
        );
    end generate main_bank;

end architecture behaviour;

As you can see the spacing in reg : A_REG_MOD is too long for no apparent reason.

Issue 2: Also from this code, as you can see that the key words port map are split over two lines (which should not be the case).

Issue 3: The ports in the port map (); section are not indented.

Issue 4: The opening bracket of the port map (); section doesn't go in a new line. Either an option should be created or it should always go from a new line.

The final formatting should look like this:

--
architecture behaviour of A_REG_BANK_MOD is
    -- Components
    component A_REG_MOD
        port
        (
            port_bytes_in : in data_size_selector
        );
    end component A_REG_MOD;

begin

    main_bank : for i in 0 to S_REG_BANK_SIZE - 1 generate
        reg : A_REG_MOD
        port map
        (
            port_bytes_in => port_bytes_in(i)
        );
    end generate main_bank;

end architecture behaviour;
g2384 commented 6 years ago

Fixed, if you think it does't, reopen this issue please