oups port (

[Franck78]

Hello my friend,

thank for fixing everything I found.

You may have introduced a problem with Port Map. It just does nothing if opening parenthesis is not on same line !

Library ieee;
Use ieee.std_logic_1164.All;

Architecture rtl Of System4_snd Is

    Signal RESET_L   : std_logic; -- Reset input, active low
    Signal diag_sw   : std_logic := '0'; -- Diagnostic switch, this can be brought out to a pin if desired
    Signal pia_cb1   : std_logic;

Begin
RAM : soundram 
Port Map
   (we=>Not cpu_rw,spo => ram_dout);
End rtl;

[g2384]

Fixed, finally! new version