Some questions regarding the SpyDrNet and its PD extension

[manili]

Hi all, I'm pretty much new to this project so I have some questions about it. I hope here is a good place to ask:

1. I can't understand the exact philosophy behind the SpyDrNet. What's different b/w SpyDrNet and something like Yosys? Is it going to be a reverse engineering tool to explore existing FPGA architectures?
2. There are some different tools for PD out there. For example one of the most famous is OpenRoad/OpenLane. What's different b/w SpyDrNet-Physical extension and these tools?
3. AFAIK the physical design process heavily depends on the technology node. But I did not find anything relate to that. How does the SpyDrNet-Physical extension do the PD process without the actual PDK?

Thanks a lot.

[ganeshgore]

This is indeed a correct place for such discussion. let me answer one by one

1. SpyDrNet is a structural Verilog netlist manipulation tool, SpyDrNet-Physical, an extension of SpyDrNet, performs netlist modification to ease physical design flow. On the other hand, Yosys is a synthesis tool that takes behavioral netlist and performs synthesis and tech-mapping (generating structural Verilog netlist)
2. Openroad/ Opelane is mainly a collection of place and route tools; they can certainly perform some netlist restructuring like SpyDrNet-Physical, but it's very limited
3. SpyDrNet-Physical does not perform any place and route; it just prepares netlist for physical design and generates useful data to be used during physical design; you need tools like Openroad/Innovus/ICC-II to perform place and route.

Simply based on the above discussion, this is the general dependency.

Behavioural netlist ----> YOSYS -> Spydrnet-Physical ---> OpenRoad

Hope that answers your question

[manili]

Thanks a lot for the reply Ganesh.

1. So if I understood correctly you mean, SpyDrNet would help the designer after synthesis process. For example, if Yosys chooses INV_1 from the SCL, you should replace it with INV_16 for better fanout. This process could be done either manually or using the SpyDrNet and some simple scripts to check the whole netlist for huge fanout and do the replacement, right?
2. So I understood that the SpyDrNet works post-Yosys and pre-OpenRoad. But still do not have a good understanding about the difference b/w SpyDrNet and SpyDrNet-Physical. What is the difference b/w structural Verilog netlist manipulation and netlist modification (restructuring) to ease physical design flow? Aren't they both doing the same thing? Maybe some simple examples could solve the misunderstandings...

Please, accept my apologies for asking silly questions...

[ganeshgore]

No need of apology these are all valid questions.

1. Changing the size of the buffer is one of valid testcase, but here we are doing far more complex manipulations for example merging two independent designs, generating tiles, creating feedthrough etc. You can see the example sections in the documentation to see few such examples

2. SpyDrNet is generic project for netlist manipulation . It can be used in many different scenarios. SpyDrNet-Physical just an extension to that which performs netlist manipulation for physical design of the FPGA