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gaph-pucrs / RS5

RV32I[M][C][V][_Zihpm][_Zkne][_Xosvm]_Zicsr processor
MIT License
9 stars 1 forks source link

Memory Writes are performed in third stage #10

Closed Willian-Nunes closed 1 year ago

Willian-Nunes commented 1 year ago

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aedalzotto commented 1 year ago

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Is this with or without MMU?

aedalzotto commented 1 year ago

@carol045 Please test this branch with coremark and berkeley COE before we approve.

Willian-Nunes commented 1 year ago

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Is this with or without MMU?

With