This pull request add a multiplication module for ASIC/FPGA. It completes the MUL (least significant bits) instruction in 3 clock cycles, and MULH instructions in 4 clock cycles.
This also includes:
Small changes to the execution, and retire blocks to support the new multiplication module
Vivado project changes to remove the FPGA DSPs multiplicators
This pull request add a multiplication module for ASIC/FPGA. It completes the MUL (least significant bits) instruction in 3 clock cycles, and MULH instructions in 4 clock cycles. This also includes: