Re-add Verilator compatibility, fix some bugs and update tests

Quality of life changes:

Avoid using bitshift operations, replacing for logic vector index access
Name all genblks
Enhance the simulation parameterization a little bit. Options should be set at tb_top.sv
Update all riscv-tests, removing old submodule and renaming from berkeley_suite
Clean up the test suite
Add parameterizable trace to Verilator top
Remove redundant RV32 and Environment parameters from mul/div and, therefore, from retire/execute
Separate ISR test from riscv-tests
Add more directions to build OS-based test
Add makefile for verilator simulation

Bugfixes:

Reorder riscv-tests to pass CSR tests and end in U-Mode
Assign PC to MEPC on exception regardless of cause
Prevent illegal instruction from changing regbank
Properly identify ecall cause, differentiating M from U-Mode ecalls
Add reset to Verilator top
Add missing bit assignments to mul module
Fix always_comb generating latch in mul module
Fix signed division overflow with a rule-based approach instead of relying on 32 cycles of division operation (only occurs when -MAX/-1)
Fix signed division by 1 zeroing-out quotient through a rule-based approach.

TODO:

[x] FIXED: The DIV and REM tests have added two ambiguous test cases each that are failing. We still need to verify what behavior is correct.
[x] Add a new ISR test which was removed from the old berkeley_suite
[x] Verilator parameterization is still pending: Verilator parameterization is done with -G flag at build-time

Left for another PR:

~Re-test Xosvm compliance with MAestro~: MAestro needs a few more memory-mapped registers to work. My idea is to create a sim/os-mmr.sv file to expose those registers in a future PR. There is no rush for this feature.

gaph-pucrs / RS5