Open gasparka opened 6 years ago
In Python one can just write x.right, but in VHDL x'right is correct. Needs to be solved via RedBaron convertor..
x.right
x'right
Current workaround is to use left_index() and right_index() functions, that also exsist in VHDL.
left_index()
right_index()
Needs to be fixed because this is confusing AF. Just spent 5 minutes myself figuring why conversion fails...
In Python one can just write
x.right
, but in VHDLx'right
is correct. Needs to be solved via RedBaron convertor..Current workaround is to use
left_index()
andright_index()
functions, that also exsist in VHDL.