Conversion: non 32 bit integers

[gasparka]

Currently integers can be used but they are always 32 bits (this is a bit of a Altera issue, sometimes it is very clear that integer can only have, lets say 4 bits), also in python wraparound behavior is not simulated.

It would be useful to specify integer size of register, for example:

def __init__(self):
    self.ireg = Int(init_value, min=0, max=16)

Implementation could be in metaclass to just remove the Int wrapper, alternative is to fully implement the Int class for all operator overloads (like intbv in MyHDL).

in VHDL, integer range can be constrained as:

subtype ireg_t is integer 0 to 16;

I have tested this in Quartus and it works well.

[gasparka]

This can be delayed as it is just an optimization, price for critical path is quite big so can become relevant.