For some reason i am not converting the power to dB in the FPGA. Power values need to take the 36 bit fixed-point format to accurately represent low power FFT bins. Converting to dB would easily allow usage of 18 bit format, which should clear out lot of confusion and save precious resources.
In addition, currently the 32 bit USB interface is used to send 1 power sample per clock. With dB values i could probably pack 4 values (8bit sample - 7 bits for integer part (0..-128 dB) and 1 bit for fractional part). So current data-rate of 2.5MB/s could go down to 0.625MB/s just like that.
For some reason i am not converting the power to dB in the FPGA. Power values need to take the 36 bit fixed-point format to accurately represent low power FFT bins. Converting to dB would easily allow usage of 18 bit format, which should clear out lot of confusion and save precious resources.
In addition, currently the 32 bit USB interface is used to send 1 power sample per clock. With dB values i could probably pack 4 values (8bit sample - 7 bits for integer part (0..-128 dB) and 1 bit for fractional part). So current data-rate of 2.5MB/s could go down to 0.625MB/s just like that.
Worth doing someday.