Add FuseSoC support

[olofk]

This adds support for building for the icebreaker board, linting with verilator or to use as dependency for other FuseSoC cores. To try building or linting first register the core library temporarily (by running with fusesoc --cores-root=/path/to/repo ...) or permanently (by running fusesoc library add csi2 /path/to/repo first)

Once core is registered, run fusesoc run --target=icebreaker csi2 to build the icebreaker example or fusesoc run --target=lint csi2 to run verilator in lint mode

[olofk]

Forgot to add a few notes:

The default target is used when a core is used as a dependency from another core. This means that any core depending on csi2 will get the iCE40-specific files csi_rx_ice40.v. Ideally I would prefer to lift out the tech-specific buffers to the icebreaker top instead, so that the link layer will be tech-agnostic and can be used with other vendors. Happy to open a PR for that if you are interested

[daveshah1]

Thanks for adding this! The reason that the link layer is ice40 specific is that most larger fpga architectures will ideally need more than the buffers changed in order to take advantage of SERDES, hard clock dividers, input delay blocks, etc.