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gatecat / CSI2Rx

Open Source 4k CSI-2 Rx core for Xilinx FPGAs
MIT License
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IO standard interface problem #3

Open Takayama-Lissajous opened 5 years ago

Takayama-Lissajous commented 5 years ago

I have adopt about different IO standard.

MIPI CSI 2 has 200mv swing voltage at HS mode(SLVS200)

but, is it possible to capture these low voltage differential signal with FPGA?

I think that FPGA lvds 2.5V VCCIO IO standard doesn't capture these low voltage differential signal(MIPI)

I reviewed Kicad board design. but I can't find any level shifter IC. Clock lane and data lanes connected directly LVDS IO pads...

daveshah1 commented 5 years ago

In practice, I have always found that LVDS inputs on FPGAs support a low enough differential swing that they receive MIPI signals fine. This has been tested on Virtex-6, Kintex-7 and iCE40.

Some FPGAs do have dedicated MIPI input support, such as the ECP5 and UltraScale+, but the main use of that would be being able to receive both the LP and HS signals.