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gatecat / CSI2Rx

Open Source 4k CSI-2 Rx core for Xilinx FPGAs
MIT License
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RocketIO usage and IO standards #6

Open luxapana opened 2 years ago

luxapana commented 2 years ago

Hello I have two questions.

  1. D-PHY spec operates in two modes, HS and low power which use different IO standards such as differential and single ended. How can we support this in an FPGA?
  2. Any issue you see in trying to use RocketIO primitives available in virtex-2 pro devices? Thanks