Open kazkojima opened 2 years ago
We at Libre-SOC encountered this bug before, when trying to build microwatt, a workaround is to tell yosys to not generate CARRY4 at all with synth_xilinx -nocarry
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cc @toshywoshy
Thanks. That would certainly be a workaround. It would disable fast carry chains, which is a bit damaging for long bit-length additions, though. I ran into this issue with an x25519 calculation and -nocarry reduced the max clock freq. by ~1/3.
Luke (the person at Libre-SOC who originally encountered this bug) thinks this bug is best fixed fixed by making yosys split long carry4 chains. imho vpr and nextpnr-xilinx are where that would be handled since they know the details of how many carry4 blocks are available and should be able to insert the necessary routing between them. imho yosys is the wrong place to try to fix that.
additional context: https://libre-soc.org/irclog/%23libre-soc.2022-03-11.log.html#t2022-03-11T18:23:08
Ok if yosys can solve the problem during synthesis, though it seems more natural to resolve that during placement. I found that the split_carry_chain() in nextpnr/ecp5/pack.cc splits the carry chain into multiple legal chains based on the chip information. There appears to be a quite similar function in nextpnr/ice40/chains.cc.
Hi,
A test case which is a 256-bit version of the carry stress test in SymbiFlow/f4pga-arch-defs
which causes a hang up of HeAP placer. SA placer fails with
It seems that all xc7 have no CARRY4 at grid_y which is a multiple of 26, as far as I've checked prjxray/database tilegrid.json files. gdb shows that that hang up happens in placer_heap.cc:legalise_placement_strict() looking for vertically contiguous chain of length > 25. The patch below works for me, though I can test it for one kintex-7 target only.