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gatecat / nextpnr-xilinx

Experimental flows using nextpnr for Xilinx devices
ISC License
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Sync upstream #56

Closed mmicko closed 1 year ago

mmicko commented 1 year ago

Hi @gatecat, I have done API adaptation of nextpnr-xilinx to mainline nextpnr. There are couple of things missing like https://github.com/gatecat/nextpnr-xilinx/commit/1b587cb521e7c0bd775f371a9f261ea200e06462 parts not being present in mainline nextpnr repository. Testing will be needed of course, but for now looking for feedback if there is anything obviously wrong in last commit (first is removal of old and adding new nextpnr mainline code). Also @hansfbaier please check if this makes it easier for you as well.

To be applied upstream: https://github.com/gatecat/nextpnr-xilinx/commit/c21f5e2b7d211e980bc75bd66722d6d141720969

hansfbaier commented 1 year ago

@mmicko I am excited to see this moving upstream. That would mean I could try new routing algorithms, because router2 seemed to hang for some configurations of a LiteX/DDR3 SoC I tried to build.

mmicko commented 1 year ago

@hansfbaier still working on cleanup and making it actually work, but idea is to at least keep it up to date with upstream one. it was too long out of sync so there are lot of changes to be done, and also as you pointed out lot of new improvements were not back ported

hansfbaier commented 1 year ago

@mmicko I am very much looking forward to the changes: Currently the maximum viable yosys version with nextpnr-xilinx is 0.17, because later versions generate a block RAM primitive that nextpnr-xilinx does not yet understand.

hansfbaier commented 1 year ago

@mmicko I rebased my work on your branch yesterday (https://github.com/kintex-chatter/nextpnr-xilinx/tree/sync_upstream), and I get a failed assert while routing (building a LiteX design), which I will have to look into.

mmicko commented 1 year ago

@hansfbaier thanks, there were just too many changes how router and placer work between main repo and this one, was looking if I made some conversion change, but found nothing so far :(

hansfbaier commented 1 year ago

@mmicko I just updated to current xilinx-upstream in my branch, and building this blinky fails:

[...]
reserving wires for arc 0 ($auto$alumacc.cc:485:replace_alu$1614.genblk1.slice[3].genblk1.carry4$split$muxcy0$PACKED_CARRY4$.S3) of net r_count[15]$legal$61
      SITEWIRE/SLICE_X1Y120/D6LUT_O6
reserving wires for arc 0 ($auto$alumacc.cc:485:replace_alu$1614.genblk1.slice[3].genblk1.carry4$split$muxcy0$PACKED_CARRY4$.DI2) of net $PACKER_GND_NET$legal$59
      SITEWIRE/SLICE_X1Y120/CCY0_OUT
      SITEWIRE/SLICE_X1Y120/CX
      CLBLL_L_X2Y120/CLBLL_L_CX
      INT_L_X2Y120/BYP_L2
      INT_L_X2Y120/BYP_ALT2
reserving wires for arc 0 ($auto$alumacc.cc:485:replace_alu$1614.genblk1.slice[3].genblk1.carry4$split$muxcy0$PACKED_CARRY4$.S2) of net r_count[14]$legal$57
      SITEWIRE/SLICE_X1Y120/C6LUT_O6
ERROR: attempting to reserve src wire 'SITEWIRE/SLICE_X1Y120/D6LUT_O6' for nets 'r_count[15]$legal$61' and '$PACKER_GND_NET$legal$55'

I also tried with your original branch and get the same error, this would rule out an error introduced by my rebase.

mmicko commented 1 year ago

@hansfbaier This is exactly what I get as well. Guess this will need @gatecat to take a look, since placer and router changed a lot meanwhile.

hansfbaier commented 1 year ago

New PnR would be great. The old one falls apart quite quickly if things get a little congested. LiteX memtest with BRAMs fails already with 128kB. 64kB are still fine

hansfbaier commented 1 year ago

@mmicko The routing algorithm is probably not the problem. I just tried router1 and its error message seems to make more sense:

ERROR: Wire SITEWIRE/SLICE_X1Y116/C6LUT_O6 is used as source and sink in different nets: r_count[23]$legal$93 vs r_count[22]$legal$89 (0)

It looks like the code that decides what gets wired up to what is broken. In other words: The netlist seems to be messed up.

gatecat commented 1 year ago

I've had a quick look through the patch at areas likely to cause problems here (in particular, the fixupPlacement() function that ensures fracturable LUT pins don't overlap before routing them) and can't immediately see the problem. The carry legalisation code is another place to look.

hansfbaier commented 1 year ago

@mmicko Some progress hunting down the bug. With router1 the error message is:

ERROR: Wire SITEWIRE/SLICE_X1Y120/C6LUT_O6 is used as source and sink in different nets: r_count[17]$legal$69 vs r_count[18]$legal$73 (0)

but the X-coordinate of the slice is actually different for those: image So somehow the code seems to ignore the X coordinate and think they are the same bel. Looking at the nets pre routing, we have:

>>> print(pr_ni(n17))
net: r_count[17]$legal$69
  driver: PortRef: r_count[17]$LUT$70 => O6
  users: [ 'PortRef: '
  '$auto$alumacc.cc:485:replace_alu$1614.genblk1.slice[4].genblk1.carry4$split$muxcy0$PACKED_CARRY4$ '
  '=> S1']
  wires: []
>>> print(pr_ni(n18))
net: r_count[18]$legal$73
  driver: PortRef: r_count[18]$LUT$74 => O6
  users: [ 'PortRef: '
  '$auto$alumacc.cc:485:replace_alu$1614.genblk1.slice[4].genblk1.carry4$split$muxcy0$PACKED_CARRY4$ '
  '=> S2']
  wires: []
>>>

But that actually should not be a problem, because those nets are connected to different ports of the using cell:

Cell: $auto$alumacc.cc:485:replace_alu$1614.genblk1.slice[4].genblk1.carry4$split$muxcy0$PACKED_CARRY4$
type: CARRY4
bel: SLICE_X1Y120/CARRY4

params:

attrs:
BEL_STRENGTH: 00000000000000000000000000000001
NEXTPNR_BEL: SLICE_X1Y120/CARRY4
X_ORIG_PORT_CIN: CI
X_ORIG_PORT_CYINIT: CYINIT
X_ORIG_PORT_DI0: DI[0]
X_ORIG_PORT_S0: S[0]
X_ORIG_PORT_CO0: CO[0]
X_ORIG_PORT_O0: O[0]
X_ORIG_PORT_DI1: DI[1]
X_ORIG_PORT_S1: S[1]
X_ORIG_PORT_CO1: CO[1]
X_ORIG_PORT_O1: O[1]
X_ORIG_PORT_DI2: DI[2]
X_ORIG_PORT_S2: S[2]
X_ORIG_PORT_CO2: CO[2]
X_ORIG_PORT_O2: O[2]
X_ORIG_PORT_DI3: DI[3]
X_ORIG_PORT_S3: S[3]
X_ORIG_PORT_CO3: CO[3]
X_ORIG_PORT_O3: O[3]
X_ORIG_TYPE: CARRY4

ports:
CIN: PortType.PORT_IN
O3: PortType.PORT_OUT
CO3: PortType.PORT_OUT
S3: PortType.PORT_IN
DI3: PortType.PORT_IN
O2: PortType.PORT_OUT
CO2: PortType.PORT_OUT
S2: PortType.PORT_IN
DI2: PortType.PORT_IN
O1: PortType.PORT_OUT
CO1: PortType.PORT_OUT
S1: PortType.PORT_IN
DI1: PortType.PORT_IN
O0: PortType.PORT_OUT
CO0: PortType.PORT_OUT
S0: PortType.PORT_IN
CYINIT: PortType.PORT_IN
DI0: PortType.PORT_IN

IMHO for pre-routing this seems to look good. Only the choice of wires does not seem to distinguish the X coordinate.

hansfbaier commented 1 year ago

@mmicko I also noticed in this branch the link time increased by many times, giving a very high turnaround time for the edit-compile-test cycle.

mmicko commented 1 year ago

@hansfbaier regarding link times, just add -DUSE_IPO=OFF to cmake options, this will help regarding link time.

Regarding changes is how placement and routing have changed meanwhile, guess input from @gatecat is needed.

hansfbaier commented 1 year ago

@mmicko Thanks!

gatecat commented 1 year ago

The placement issue should now be fixed. I also had to disable the netShareWeight stuff as it is broken upstream (I don't think other arches use it in the end), but that was only a small benefit anyway.

The previous #ifdef ARCH_XILINX stuff in router2 should hopefully not be needed with my last patch as router2 can better handle these sorts of things at a core level. If there are still issues with big designs, let me know and I will see how things could be improved more generally.

mmicko commented 1 year ago

thanks @gatecat, can confirm it runs fine (not tested on real hw still)

One thing that is not up-streamed are changes for BBA, everything else is in sync.

gatecat commented 1 year ago

I have also just run my bulk refactor scripts from the other arches to bring coding style a bit more up to date with the rest of nextpnr. As the set of constids changed you'll need to rebuild any bbas after this.

mmicko commented 1 year ago

@gatecat just added this one commit to sync with latest upstream

mmicko commented 1 year ago

Sorry I missed few things that should not be touched (in router2 and designwidget) so forced pushed, but seems something is wrong after refactoring

getting next error now

terminate called after throwing an instance of 'nextpnr_xilinx::assertion_failure'
  what():  Assertion failure: int(ctx->idstring_idx_to_str->size()) == idx (/home/micko/src/mmicko/nextpnr-xilinx/common/kernel/idstring.cc:46)
gatecat commented 1 year ago

did you rebuild your bbas?

mmicko commented 1 year ago

all fine, sorry. too much back-forward so did not do it last time :(

hansfbaier commented 1 year ago

@gatecat I built this design: https://github.com/kintex-chatter/demo-projects/tree/main/litex-ddr-stlv7325 with this database: https://github.com/kintex-chatter/db-workspace-for-kintex7 and latest nextpnr-xilinx-meta. Build was successful, but UART only outputs garbage instead of the LiteX boot message, probably timing fail.

hansfbaier commented 1 year ago

@gatecat I built a variation of this design, where the router loop does not terminate:

Info: Running main router loop...
Info:     iter=1 wires=299168 overused=17679 overuse=18980 archfail=NA
Info:     iter=2 wires=314129 overused=1452 overuse=1453 archfail=NA
Info:     iter=3 wires=314967 overused=177 overuse=177 archfail=NA
Info:     iter=4 wires=315075 overused=65 overuse=65 archfail=NA
Info:     iter=5 wires=315105 overused=33 overuse=33 archfail=NA
Info:     iter=6 wires=315118 overused=25 overuse=25 archfail=NA
Info:     iter=7 wires=315126 overused=17 overuse=17 archfail=NA
Info:     iter=8 wires=315129 overused=13 overuse=13 archfail=NA
Info:     iter=9 wires=315127 overused=13 overuse=13 archfail=NA
Info:     iter=10 wires=315130 overused=11 overuse=11 archfail=NA
Info:     iter=11 wires=315134 overused=11 overuse=11 archfail=NA
Info:     iter=12 wires=315134 overused=8 overuse=8 archfail=NA
Info:     iter=13 wires=315136 overused=7 overuse=7 archfail=NA
Info:     iter=14 wires=315136 overused=7 overuse=7 archfail=NA
Info:     iter=15 wires=315139 overused=6 overuse=6 archfail=NA
Info:     iter=16 wires=315138 overused=5 overuse=5 archfail=NA
Info:     iter=17 wires=315139 overused=4 overuse=4 archfail=NA
Info:     iter=18 wires=315139 overused=3 overuse=3 archfail=NA
Info:     iter=19 wires=315139 overused=3 overuse=3 archfail=NA
Info:     iter=20 wires=315139 overused=3 overuse=3 archfail=NA
Info:     iter=21 wires=315139 overused=3 overuse=3 archfail=NA
Info:     iter=22 wires=315139 overused=3 overuse=3 archfail=NA
Info:     iter=23 wires=315139 overused=3 overuse=3 archfail=NA
Info:     iter=24 wires=315139 overused=3 overuse=3 archfail=NA
Info:     iter=25 wires=315139 overused=3 overuse=3 archfail=NA
Info:     iter=26 wires=315139 overused=3 overuse=3 archfail=NA
Info:     iter=27 wires=315139 overused=3 overuse=3 archfail=NA
Info:     iter=28 wires=315139 overused=3 overuse=3 archfail=NA
Info:     iter=29 wires=315139 overused=3 overuse=3 archfail=NA
Info:     iter=30 wires=315139 overused=3 overuse=3 archfail=NA
Info:     iter=31 wires=315139 overused=3 overuse=3 archfail=NA
Info:     iter=32 wires=315139 overused=3 overuse=3 archfail=NA
[...]
hansfbaier commented 1 year ago

Here is a buildable project (with synthesized json). litex-ddr-stlv7325.tar.gz

gatecat commented 1 year ago

Thanks for testing this! It might take a few days for me to look at this in detail; but somethings you could do to help if you have time in the meanwhile:

I'm also curious how runtime performance is comparing in general against the previous nextpnr-xilinx?

hansfbaier commented 1 year ago

@gatecat the design from the tarball above runs well at 100MHz, when I use router1

     /____/_/\__/\__/_/|_|
   Build your hardware, easily!

 (c) Copyright 2012-2022 Enjoy-Digital
 (c) Copyright 2007-2015 M-Labs

 BIOS built on Feb  2 2023 12:08:07
 BIOS CRC passed (f7aec54c)

 LiteX git sha1: 8b14e649

--=============== SoC ==================--
CPU:        VexRiscv_Min @ 100MHz
BUS:        WISHBONE 32-bit @ 4GiB
CSR:        32-bit data
ROM:        128.0KiB
SRAM:       8.0KiB
SDRAM:      64.0MiB 16-bit @ 800MT/s (CL-6 CWL-5)
MAIN-RAM:   256.0MiB

--========== Initialization ============--
Initializing SDRAM @0x40000000...
Switching SDRAM to software control.
Write leveling:
  tCK equivalent taps: 32
  Cmd/Clk scan (0-16)
  |1111111111110000| best: 0
  Setting Cmd/Clk delay to 0 taps.
  Data scan:
  m0: |000000000111111111111111| delay: 09
  m1: |000000000111111111111111| delay: 09
Write latency calibration:
m0:0 m1:0 
Write DQ-DQS training:
m0: |000111111111111110000000000000000| delays: 09+-06
m1: |001111111111111111000000000000000| delays: 09+-07
Read leveling:
  m0, b00: |00000000000000000000000000000000| delays: -
  m0, b01: |00000000000000000000000000000000| delays: -
  m0, b02: |10111111111100000000000000000000| delays: 06+-04
  m0, b03: |00000000000000001111111111110000| delays: 20+-05
  m0, b04: |00000000000000000000000000000000| delays: -
  m0, b05: |00000000000000000000000000000000| delays: -
  m0, b06: |00000000000000000000000000000000| delays: -
  m0, b07: |00000000000000000000000000000000| delays: -
  best: m0, b03 delays: 21+-05
  m1, b00: |00000000000000000000000000000000| delays: -
  m1, b01: |00000000000000000000000000000000| delays: 01+-00
  m1, b02: |00111111111111110000000000000000| delays: 08+-05
  m1, b03: |00000000000000000100011111111101| delays: 24+-06
  m1, b04: |00000000000000000000000000000000| delays: -
  m1, b05: |00000000000000000000000000000000| delays: -
  m1, b06: |00000000000000000000000000000000| delays: -
  m1, b07: |00000000000000000000000000000000| delays: -
  best: m1, b02 delays: 08+-05
Switching SDRAM to hardware control.
Memtest at 0x40000000 (2.0MiB)...
  Write: 0x40000000-0x40200000 2.0MiB     
   Read: 0x40000000-0x40200000 2.0MiB     
Memtest OK
Memspeed at 0x40000000 (Sequential, 2.0MiB)...
  Write speed: 72.5MiB/s
   Read speed: 26.1MiB/s

--============== Boot ==================--
Booting from serial...
Press Q or ESC to abort boot completely.
sL5DdSMmkekro
             Timeout
No boot medium found

--============= Console ================--
hansfbaier commented 1 year ago

@gatecat In the tarball design above, when using router2, it loops over these nets:

[...]
Routing arc 0 of net '$techmap286498$abc$284630$lut$aiger284629$12910.A[5]' (188, 253) -> (188, 254)
Routing arc 0 of net '$techmap286498$abc$284630$lut$aiger284629$12910.A[5]' (is_bb = 1) took 0.000386s
Routing arc 0 of net '$techmap286498$abc$284630$lut$aiger284629$12910.A[5]' (188, 253) -> (188, 254)
Routing arc 0 of net '$techmap286498$abc$284630$lut$aiger284629$12910.A[5]' (is_bb = 1) took 0.000658s
Routing arc 0 of net 'soc_sdram_bankmachine7_row[7]' (188, 254) -> (188, 254)
Routing arc 0 of net 'soc_sdram_bankmachine7_row[7]' (is_bb = 1) took 0.000325s
Routing arc 0 of net '$techmap286498$abc$284630$lut$aiger284629$12910.A[5]' (188, 253) -> (188, 254)
Routing arc 0 of net '$techmap286498$abc$284630$lut$aiger284629$12910.A[5]' (is_bb = 1) took 0.000636s
Routing arc 0 of net 'soc_sdram_bankmachine7_row[7]' (188, 254) -> (188, 254)
Routing arc 0 of net 'soc_sdram_bankmachine7_row[7]' (is_bb = 1) took 0.000369s
Routing arc 0 of net '$techmap286498$abc$284630$lut$aiger284629$12910.A[5]' (188, 253) -> (188, 254)
Routing arc 0 of net '$techmap286498$abc$284630$lut$aiger284629$12910.A[5]' (is_bb = 1) took 0.000472s
Routing arc 0 of net 'soc_sdram_bankmachine7_row[7]' (188, 254) -> (188, 254)
Routing arc 0 of net 'soc_sdram_bankmachine7_row[7]' (is_bb = 1) took 0.000346s
Routing arc 0 of net 'soc_sdram_bankmachine7_row[7]' (188, 254) -> (188, 254)
Routing arc 0 of net 'soc_sdram_bankmachine7_row[7]' (is_bb = 1) took 0.000461s
Routing arc 0 of net '$techmap286498$abc$284630$lut$aiger284629$12910.A[5]' (188, 253) -> (188, 254)
Routing arc 0 of net '$techmap286498$abc$284630$lut$aiger284629$12910.A[5]' (is_bb = 1) took 0.000477s
Routing arc 0 of net '$techmap286498$abc$284630$lut$aiger284629$12910.A[5]' (188, 253) -> (188, 254)
Routing arc 0 of net '$techmap286498$abc$284630$lut$aiger284629$12910.A[5]' (is_bb = 1) took 0.000517s
Routing arc 0 of net 'soc_sdram_bankmachine7_row[7]' (188, 254) -> (188, 254)
Routing arc 0 of net 'soc_sdram_bankmachine7_row[7]' (is_bb = 1) took 0.000343s
Routing arc 0 of net 'soc_sdram_bankmachine7_row[7]' (188, 254) -> (188, 254)
Routing arc 0 of net 'soc_sdram_bankmachine7_row[7]' (is_bb = 1) took 0.000499s
Routing arc 0 of net '$techmap286498$abc$284630$lut$aiger284629$12910.A[5]' (188, 253) -> (188, 254)
Routing arc 0 of net '$techmap286498$abc$284630$lut$aiger284629$12910.A[5]' (is_bb = 1) took 0.000312s
Routing arc 0 of net '$techmap286498$abc$284630$lut$aiger284629$12910.A[5]' (188, 253) -> (188, 254)
Routing arc 0 of net '$techmap286498$abc$284630$lut$aiger284629$12910.A[5]' (is_bb = 1) took 0.000512s
Routing arc 0 of net 'soc_sdram_bankmachine7_row[7]' (188, 254) -> (188, 254)
Routing arc 0 of net 'soc_sdram_bankmachine7_row[7]' (is_bb = 1) took 0.000400s
Routing arc 0 of net 'soc_sdram_bankmachine7_row[7]' (188, 254) -> (188, 254)
Routing arc 0 of net 'soc_sdram_bankmachine7_row[7]' (is_bb = 1) took 0.000453s
Routing arc 0 of net '$techmap286498$abc$284630$lut$aiger284629$12910.A[5]' (188, 253) -> (188, 254)
Routing arc 0 of net '$techmap286498$abc$284630$lut$aiger284629$12910.A[5]' (is_bb = 1) took 0.000358s
Routing arc 0 of net '$techmap286498$abc$284630$lut$aiger284629$12910.A[5]' (188, 253) -> (188, 254)
Routing arc 0 of net '$techmap286498$abc$284630$lut$aiger284629$12910.A[5]' (is_bb = 1) took 0.000391s
Routing arc 0 of net 'soc_sdram_bankmachine7_row[7]' (188, 254) -> (188, 254)
Routing arc 0 of net 'soc_sdram_bankmachine7_row[7]' (is_bb = 1) took 0.000310s
Routing arc 0 of net 'soc_sdram_bankmachine7_row[7]' (188, 254) -> (188, 254)
Routing arc 0 of net 'soc_sdram_bankmachine7_row[7]' (is_bb = 1) took 0.000368s
Routing arc 0 of net '$techmap286498$abc$284630$lut$aiger284629$12910.A[5]' (188, 253) -> (188, 254)
Routing arc 0 of net '$techmap286498$abc$284630$lut$aiger284629$12910.A[5]' (is_bb = 1) took 0.000427s
Routing arc 0 of net 'soc_sdram_bankmachine7_row[7]' (188, 254) -> (188, 254)
Routing arc 0 of net 'soc_sdram_bankmachine7_row[7]' (is_bb = 1) took 0.000458s
Routing arc 0 of net '$techmap286498$abc$284630$lut$aiger284629$12910.A[5]' (188, 253) -> (188, 254)
Routing arc 0 of net '$techmap286498$abc$284630$lut$aiger284629$12910.A[5]' (is_bb = 1) took 0.000413s
Routing arc 0 of net '$techmap286498$abc$284630$lut$aiger284629$12910.A[5]' (188, 253) -> (188, 254)
Routing arc 0 of net '$techmap286498$abc$284630$lut$aiger284629$12910.A[5]' (is_bb = 1) took 0.000515s
Routing arc 0 of net 'soc_sdram_bankmachine7_row[7]' (188, 254) -> (188, 254)
Routing arc 0 of net 'soc_sdram_bankmachine7_row[7]' (is_bb = 1) took 0.000299s
Routing arc 0 of net 'soc_sdram_bankmachine7_row[7]' (188, 254) -> (188, 254)
Routing arc 0 of net 'soc_sdram_bankmachine7_row[7]' (is_bb = 1) took 0.000353s
Routing arc 0 of net '$techmap286498$abc$284630$lut$aiger284629$12910.A[5]' (188, 253) -> (188, 254)
Routing arc 0 of net '$techmap286498$abc$284630$lut$aiger284629$12910.A[5]' (is_bb = 1) took 0.000417s
Routing arc 0 of net '$techmap286498$abc$284630$lut$aiger284629$12910.A[5]' (188, 253) -> (188, 254)
Routing arc 0 of net '$techmap286498$abc$284630$lut$aiger284629$12910.A[5]' (is_bb = 1) took 0.000447s
Routing arc 0 of net 'soc_sdram_bankmachine7_row[7]' (188, 254) -> (188, 254)
Routing arc 0 of net 'soc_sdram_bankmachine7_row[7]' (is_bb = 1) took 0.000285s
Routing arc 0 of net 'soc_sdram_bankmachine7_row[7]' (188, 254) -> (188, 254)
Routing arc 0 of net 'soc_sdram_bankmachine7_row[7]' (is_bb = 1) took 0.000394s
Routing arc 0 of net '$techmap286498$abc$284630$lut$aiger284629$12910.A[5]' (188, 253) -> (188, 254)
Routing arc 0 of net '$techmap286498$abc$284630$lut$aiger284629$12910.A[5]' (is_bb = 1) took 0.000312s
[...]

They seem always to be about the regular logic slices:

   Routed (explored 18 wires):       fwd wire: INT_R_X77Y105/SR1BEG3 (curr 0 hist 1.000000 share 1)
         fwd pip: INT_R_X77Y105/219.455 (187, 254)
      fwd wire: INT_R_X77Y105/LOGIC_OUTS20 (curr 1 hist 5636.000000 share 1)
         fwd pip: CLBLM_R_X77Y105/192.125 (188, 254)
      fwd wire: CLBLM_R_X77Y105/CLBLM_M_AMUX (curr 1 hist 5636.000000 share 1)
         fwd pip: CLBLM_R_X77Y105/404.192 (188, 254)
      fwd wire: SITEWIRE/SLICE_X126Y105/AMUX (curr 1 hist 5636.000000 share 1)
         fwd pip: SITEPIP/SLICE_X126Y105/AOUTMUX/A5FF_Q (188, 254)
      fwd wire: SITEWIRE/SLICE_X126Y105/A5FF_Q (curr 0 hist 1.000000 share 5636)
         bwd pip: INT_R_X77Y105/460.185 (187, 254)
      bwd wire: INT_R_X77Y105/IMUX8 (curr 0 hist 2.000000 share 1)
         bwd pip: CLBLM_R_X77Y105/98.189 (188, 254)
      bwd wire: CLBLM_R_X77Y105/CLBLM_M_A5 (curr 0 hist 2.000000 share 1)
         bwd pip: CLBLM_R_X77Y105/189.326 (188, 254)
      bwd wire: SITEWIRE/SLICE_X126Y105/A3 (curr 0 hist 1.000000 share 1)

In a little different design (still with DDR3 SDRAM, but with lower clock freq), it loops here:

[...]
Routing arc 0 of net 'soc_reset_counter[1]' (219, 305) -> (219, 305)
Routing arc 0 of net 'soc_reset_counter[1]' (is_bb = 1) took 0.006339s
Routing arc 2 of net 'soc_reset_counter[1]' (219, 305) -> (219, 305)
Routing arc 0 of net 'soc_reset_counter[1]' (219, 305) -> (219, 305)
Routing arc 0 of net 'soc_reset_counter[1]' (is_bb = 1) took 0.003512s
Routing arc 2 of net 'soc_reset_counter[1]' (219, 305) -> (219, 305)
Routing arc 0 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (219, 305) -> (219, 305)
Routing arc 0 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (is_bb = 1) took 0.000557s
Routing arc 1 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (219, 305) -> (219, 305)
Routing arc 2 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (219, 305) -> (219, 305)
Routing arc 0 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (219, 305) -> (219, 305)
Routing arc 0 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (is_bb = 1) took 0.000854s
Routing arc 1 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (219, 305) -> (219, 305)
Routing arc 2 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (219, 305) -> (219, 305)
Routing arc 0 of net 'soc_reset_counter[1]' (219, 305) -> (219, 305)
Routing arc 0 of net 'soc_reset_counter[1]' (is_bb = 1) took 0.006759s
Routing arc 2 of net 'soc_reset_counter[1]' (219, 305) -> (219, 305)
Routing arc 0 of net 'soc_reset_counter[1]' (219, 305) -> (219, 305)
Routing arc 0 of net 'soc_reset_counter[1]' (is_bb = 1) took 0.005198s
Routing arc 2 of net 'soc_reset_counter[1]' (219, 305) -> (219, 305)
Routing arc 0 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (219, 305) -> (219, 305)
Routing arc 0 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (is_bb = 1) took 0.000466s
Routing arc 1 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (219, 305) -> (219, 305)
Routing arc 2 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (219, 305) -> (219, 305)
Routing arc 0 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (219, 305) -> (219, 305)
Routing arc 0 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (is_bb = 1) took 0.000905s
Routing arc 1 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (219, 305) -> (219, 305)
Routing arc 2 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (219, 305) -> (219, 305)
Routing arc 0 of net 'soc_reset_counter[1]' (219, 305) -> (219, 305)
Routing arc 0 of net 'soc_reset_counter[1]' (is_bb = 1) took 0.005179s
Routing arc 2 of net 'soc_reset_counter[1]' (219, 305) -> (219, 305)
Routing arc 0 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (219, 305) -> (219, 305)
Routing arc 0 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (is_bb = 1) took 0.000518s
Routing arc 1 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (219, 305) -> (219, 305)
Routing arc 2 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (219, 305) -> (219, 305)
Routing arc 0 of net 'soc_reset_counter[1]' (219, 305) -> (219, 305)
Routing arc 0 of net 'soc_reset_counter[1]' (is_bb = 1) took 0.007041s
Routing arc 2 of net 'soc_reset_counter[1]' (219, 305) -> (219, 305)
Routing arc 0 of net 'soc_reset_counter[1]' (219, 305) -> (219, 305)
Routing arc 0 of net 'soc_reset_counter[1]' (is_bb = 1) took 0.001796s
Routing arc 2 of net 'soc_reset_counter[1]' (219, 305) -> (219, 305)
Routing arc 0 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (219, 305) -> (219, 305)
Routing arc 0 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (is_bb = 1) took 0.000581s
Routing arc 1 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (219, 305) -> (219, 305)
Routing arc 2 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (219, 305) -> (219, 305)
Routing arc 0 of net 'soc_reset_counter[1]' (219, 305) -> (219, 305)
Routing arc 0 of net 'soc_reset_counter[1]' (is_bb = 1) took 0.005478s
Routing arc 2 of net 'soc_reset_counter[1]' (219, 305) -> (219, 305)
Routing arc 0 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (219, 305) -> (219, 305)
Routing arc 0 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (is_bb = 1) took 0.000446s
Routing arc 1 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (219, 305) -> (219, 305)
Routing arc 2 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (219, 305) -> (219, 305)
Routing arc 0 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (219, 305) -> (219, 305)
Routing arc 0 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (is_bb = 1) took 0.000939s
Routing arc 1 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (219, 305) -> (219, 305)
Routing arc 2 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (219, 305) -> (219, 305)
Routing arc 0 of net 'soc_reset_counter[1]' (219, 305) -> (219, 305)
Routing arc 0 of net 'soc_reset_counter[1]' (is_bb = 1) took 0.004593s
Routing arc 2 of net 'soc_reset_counter[1]' (219, 305) -> (219, 305)
Routing arc 0 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (219, 305) -> (219, 305)
Routing arc 0 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (is_bb = 1) took 0.000561s
Routing arc 1 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (219, 305) -> (219, 305)
Routing arc 2 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (219, 305) -> (219, 305)
Routing arc 0 of net 'soc_reset_counter[1]' (219, 305) -> (219, 305)
Routing arc 0 of net 'soc_reset_counter[1]' (is_bb = 1) took 0.002852s
Routing arc 2 of net 'soc_reset_counter[1]' (219, 305) -> (219, 305)
Routing arc 0 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (219, 305) -> (219, 305)
Routing arc 0 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (is_bb = 1) took 0.000797s
Routing arc 1 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (219, 305) -> (219, 305)
Routing arc 2 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (219, 305) -> (219, 305)
Routing arc 0 of net 'soc_reset_counter[1]' (219, 305) -> (219, 305)
Routing arc 0 of net 'soc_reset_counter[1]' (is_bb = 1) took 0.005001s
Routing arc 2 of net 'soc_reset_counter[1]' (219, 305) -> (219, 305)
Routing arc 0 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (219, 305) -> (219, 305)
Routing arc 0 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (is_bb = 1) took 0.000576s
Routing arc 1 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (219, 305) -> (219, 305)
Routing arc 2 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (219, 305) -> (219, 305)
Routing arc 0 of net 'soc_reset_counter[1]' (219, 305) -> (219, 305)
Routing arc 0 of net 'soc_reset_counter[1]' (is_bb = 1) took 0.000961s
Routing arc 2 of net 'soc_reset_counter[1]' (219, 305) -> (219, 305)
[...]
Routing net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y'...
Routing arc 0 of net '$abc$280431$ne$hpcstore_stlv7325_platform.v:9071$3391_Y' (219, 305) -> (219, 305)
     crit=1.000 crit_weight=0.000
src_wire = SITEWIRE/SLICE_X147Y56/B6LUT_O6 -> dst_wire = SITEWIRE/SLICE_X147Y56/CEUSEDMUX_OUT
Info:     src (219, 305) dst (219, 305)
Info:     src (219, 305) dst (219, 305)
Info:     src (219, 305) dst (219, 305)
Info:     src (219, 305) dst (219, 305)
Info:     src (219, 305) dst (219, 305)
Info:     src (219, 305) dst (219, 305)
Info:     src (219, 305) dst (219, 305)
Info:     src (219, 305) dst (219, 305)
Info:     src (219, 305) dst (219, 305)
Info:     src (219, 305) dst (219, 305)
Info:     src (219, 305) dst (220, 305)
Info:     src (220, 305) dst (219, 305)
Info:     src (219, 305) dst (220, 305)
Info:     src (220, 305) dst (219, 305)
Info:     src (219, 305) dst (220, 305)
Info:     src (219, 305) dst (220, 306)
Info:     src (219, 305) dst (214, 305)
Info:     src (219, 305) dst (215, 305)
Info:     src (219, 305) dst (215, 305)
Info:     src (219, 305) dst (220, 305)
Info:     src (219, 305) dst (220, 305)
Info:     src (219, 305) dst (220, 305)
Info:     src (219, 305) dst (220, 305)
Info:     src (219, 305) dst (220, 305)
Info:     src (219, 305) dst (220, 305)
Info:     src (219, 305) dst (215, 305)
Info:     src (219, 305) dst (220, 306)
Info:     src (219, 305) dst (220, 306)
Info:     src (219, 305) dst (220, 306)
Info:     src (219, 305) dst (220, 305)
Info:     src (219, 305) dst (215, 305)
Info:     src (219, 305) dst (220, 304)
Info:     src (219, 305) dst (220, 304)
Info:     src (219, 305) dst (220, 304)
Info:     src (219, 305) dst (220, 305)
Info:     src (219, 305) dst (4, 305)
Info:     src (219, 305) dst (220, 305)
Info:     src (219, 305) dst (220, 305)
Info:     src (219, 305) dst (220, 305)
Info:     src (224, 305) dst (219, 305)
Info:     src (231, 305) dst (219, 305)
Info:     src (221, 305) dst (219, 305)
Info:     src (221, 305) dst (219, 305)
Info:     src (220, 305) dst (219, 305)
Info:     src (219, 305) dst (219, 305)
Info:     src (219, 305) dst (219, 305)
Info:     src (219, 305) dst (219, 305)
Info:     src (219, 305) dst (219, 305)
Info:     src (219, 305) dst (219, 305)
Info:     src (219, 305) dst (219, 305)
Info:     src (221, 304) dst (219, 305)
Info:     src (224, 301) dst (219, 305)
Info:     src (220, 305) dst (219, 305)
Info:     src (220, 303) dst (219, 305)
Info:     src (220, 299) dst (219, 305)
Info:     src (220, 304) dst (219, 305)
Info:     src (215, 304) dst (219, 305)
Info:     src (214, 301) dst (219, 305)
Info:     src (221, 306) dst (219, 305)
Info:     src (224, 309) dst (219, 305)
Info:     src (220, 306) dst (219, 305)
Info:     src (220, 306) dst (219, 305)
Info:     src (220, 307) dst (219, 305)
Info:     src (220, 311) dst (219, 305)
Info:     src (215, 306) dst (219, 305)
Info:     src (214, 309) dst (219, 305)
Info:     src (215, 305) dst (219, 305)
Info:     src (215, 305) dst (219, 305)
Info:     src (214, 305) dst (219, 305)
Info:     src (210, 305) dst (219, 305)
Info:     src (224, 305) dst (219, 305)
Info:     src (231, 305) dst (219, 305)
Info:     src (221, 305) dst (219, 305)
Info:     src (221, 304) dst (219, 305)
Info:     src (220, 305) dst (219, 305)
Info:     src (219, 305) dst (219, 305)
Info:     src (219, 305) dst (219, 305)
Info:     src (219, 305) dst (219, 305)
Info:     src (219, 305) dst (219, 305)
Info:     src (219, 305) dst (219, 305)
Info:     src (219, 305) dst (219, 305)
Info:     src (221, 304) dst (219, 305)
Info:     src (224, 301) dst (219, 305)
Info:     src (220, 304) dst (219, 305)
Info:     src (220, 303) dst (219, 305)
Info:     src (220, 299) dst (219, 305)
Info:     src (220, 304) dst (219, 305)
Info:     src (215, 304) dst (219, 305)
Info:     src (214, 301) dst (219, 305)
Info:     src (221, 306) dst (219, 305)
Info:     src (224, 309) dst (219, 305)
Info:     src (220, 306) dst (219, 305)
Info:     src (220, 305) dst (219, 305)
Info:     src (220, 306) dst (219, 305)
Info:     src (220, 310) dst (219, 305)
Info:     src (215, 305) dst (219, 305)
Info:     src (214, 308) dst (219, 305)
Info:     src (215, 305) dst (219, 305)
Info:     src (215, 305) dst (219, 305)
Info:     src (214, 305) dst (219, 305)
Info:     src (210, 305) dst (219, 305)
Info:     src (219, 305) dst (219, 305)
Info:     src (220, 305) dst (219, 305)
Info:     src (220, 305) dst (219, 305)
Info:     src (219, 305) dst (219, 305)
Info:     src (220, 305) dst (219, 305)
Info:     src (220, 305) dst (219, 305)
Info:     src (219, 305) dst (221, 305)
Info:     src (219, 305) dst (221, 305)
Info:     src (219, 305) dst (221, 305)
Info:     src (219, 305) dst (221, 305)
Info:     src (219, 305) dst (221, 305)
Info:     src (219, 305) dst (221, 305)
Info:     src (219, 305) dst (224, 305)
Info:     src (219, 305) dst (224, 309)
Info:     src (219, 305) dst (220, 305)
Info:     src (219, 305) dst (215, 301)
Info:     src (219, 305) dst (221, 304)
Info:     src (219, 305) dst (221, 304)
Info:     src (219, 305) dst (221, 304)
Info:     src (219, 305) dst (221, 300)
Info:     src (219, 305) dst (224, 305)
Info:     src (219, 305) dst (224, 301)
Info:     src (219, 305) dst (224, 305)
Info:     src (219, 305) dst (224, 305)
Info:     src (219, 305) dst (224, 305)
Info:     src (219, 305) dst (224, 305)
Info:     src (219, 305) dst (219, 305)
   Routed (explored 23 wires):       fwd wire: INT_L_X90Y56/FAN_BOUNCE1 (curr 0 hist 2.000000 share 1)
         fwd pip: INT_L_X90Y56/85.93 (220, 305)
      fwd wire: INT_L_X90Y56/FAN_ALT1 (curr 0 hist 2.000000 share 1)
         fwd pip: INT_L_X90Y56/215.85 (220, 305)
      fwd wire: INT_L_X90Y56/LOGIC_OUTS_L17 (curr 1 hist 5461.000000 share 1)
         fwd pip: CLBLL_L_X90Y56/199.167 (219, 305)
      fwd wire: CLBLL_L_X90Y56/CLBLL_L_BMUX (curr 1 hist 5461.000000 share 1)
         fwd pip: CLBLL_L_X90Y56/484.199 (219, 305)
      fwd wire: SITEWIRE/SLICE_X147Y56/BMUX (curr 1 hist 5461.000000 share 1)
         fwd pip: SITEPIP/SLICE_X147Y56/BOUTMUX/B6LUT_O6 (219, 305)
      fwd wire: SITEWIRE/SLICE_X147Y56/B6LUT_O6 (curr 0 hist 1.000000 share 5461)
         bwd pip: INT_L_X90Y56/93.90 (220, 305)
      bwd wire: INT_L_X90Y56/FAN_ALT6 (curr 0 hist 1.000000 share 1)
         bwd pip: INT_L_X90Y56/90.110 (220, 305)
      bwd wire: INT_L_X90Y56/FAN_L6 (curr 0 hist 1.000000 share 1)
         bwd pip: CLBLL_L_X90Y56/50.209 (219, 305)
      bwd wire: CLBLL_L_X90Y56/CLBLL_L_CE (curr 0 hist 1.000000 share 1)
         bwd pip: CLBLL_L_X90Y56/209.486 (219, 305)
      bwd wire: SITEWIRE/SLICE_X147Y56/CE (curr 0 hist 1.000000 share 1)
         bwd pip: SITEPIP/SLICE_X147Y56/CEUSEDMUX/CE (219, 305)
      bwd wire: SITEWIRE/SLICE_X147Y56/CEUSEDMUX_OUT (curr 0 hist 1.000000 share 1)

Something in the logic slices seems to get router2 hung up.

hansfbaier commented 1 year ago

@gatecat I now built a simple soc with 32kB block RAM instead of DDR3 SDRAM (CPU is VexRiscV Minimal). Still the same situation as above.

log-part.txt.gz litex-ddr-stlv7325.tar.gz

The last 10MB of logs and the project are attached.

hansfbaier commented 1 year ago

@gatecat I built the same design with less BRAM and picorv32/femtorv32, but there router2 worked. But the design did not run. (LiteX LED chaser was running but no output on the UART)

hansfbaier commented 1 year ago

@gatecat I could reproduce the issue with femtorv32 and 64kB RAM. Log is included in the archive litex-ddr-stlv7325.tar.gz router1 is working for the same design.

gatecat commented 1 year ago

I will try and investigate the correctness issues. As for the getting stuck routing issue; it looks like the design isn't fundamentally unrouteable (e.g. not a placer bug), just the various routing heuristics aren't quite working properly. This is usually a big pain to fix reliably so I can't promise anything there.

hansfbaier commented 1 year ago

@gatecat Yes, router1 works great. Defaulting for that one in nextpnr-xilinx might be an option in the near future. How useable is awooter? Looks very interesting...

gatecat commented 1 year ago

I would hope router2 would give much better performance than router1 on xilinx, I'd really like to see router2 made to work as well.

hansfbaier commented 1 year ago

@gatecat If you give me some pointers of what to look for I could try and help with the debugging effort.

gatecat commented 1 year ago

you could start with trying to fiddle with some of the routing parameters: https://github.com/YosysHQ/nextpnr/blob/48b0025732f7b5b1b7b091691bb5a26634ae5069/common/route/router2.cc#L1487

in particular; estimate_weight, bias_cost_factor bb_margin_x and bb_margin_y (increasing bb_margin_x to 5 or 6 for xilinx might help)

gatecat commented 1 year ago

it might also be that reinstating the shared pin heuristic in the placer that I disabled because it broke upstream (issues with chain swapping, I need to look at this) might make the design easier to route.

hansfbaier commented 1 year ago

@gatecat Increasing bb_margin_x had no effect. Still need to read the CRoute paper to understand what the other parameters mean.

ept221 commented 1 year ago

@hansfbaier @mmicko What's the status of this branch? It sounds like everything works except for router2, is that correct? Does the master branch also have the same issue where routed designs fail on physical hardware, or is it just this refactored branch that has this problem? - Thanks

hansfbaier commented 1 year ago

@hansfbaier @mmicko What's the status of this branch? It sounds like everything works except for router2, is that correct? Does the master branch also have the same issue where routed designs fail on physical hardware, or is it just this refactored branch that has this problem? - Thanks

Yes I can build a LiteX design with DDR3 memory in Kintex with router1. And it works on physical hardware. Router2 very likely works on master though I have not tried it. In this branch it just gets into an endless routing loop in some designs.

ept221 commented 1 year ago

All right, I just tested a LiteX SoC with DDR3 memory for an Artix board using the non-refactored version, and both router1 and router2 produced designs which worked on the hardware.

hansfbaier commented 1 year ago

@gatecat Could we merge that and make router1 default for the time being? Because I also encounter a routing issue when using DSPs with router2 that does not exist in router1. Also because I am in sort of a dilemma of where I should base my current work (which is supporting DSP48E1) on.

gatecat commented 1 year ago

If router1 isn't performing terribly for your use cases, let's go for that for now and see if we can improve router2 down the line.

hansfbaier commented 1 year ago

It is performing quite okay so far on LiteX with DDR3 designs. The first real world use case of the toolchain will be in university education and the designs there also will very likely be smaller designs.

mmicko commented 1 year ago

@hansfbaier I have just synced with xilinx-upstream first and then updated to latest nextpnr core files, so if you can just do final checks if all is still fine and work as expected

hansfbaier commented 1 year ago

@mmicko I always get an assert fail now:

gdb --args nextpnr-xilinx --router router1 --chipdb ../chipdb/xc7k160tffg676-2.bin --xdc enclustra_mercury_kx2.xdc  --json enclustra_merc
ury_kx2.json --write enclustra_mercury_kx2_routed.json --fasm enclustra_mercury_kx2.fasm  --verbose --debug
............................................................................................
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Reading symbols from nextpnr-xilinx...
(gdb) run
Starting program: /usr/local/bin/nextpnr-xilinx --router router1 --chipdb ../chipdb/xc7k160tffg676-2.bin --xdc enclustra_mercury_kx2.xdc --json enclustra_mercury_kx2.json --write enclustra_mercury_kx2_routed.json --fasm enclustra_mercury_kx2.fasm --verbose --debug
terminate called after throwing an instance of 'nextpnr_xilinx::assertion_failure'
  what():  Assertion failure: int(ctx->idstring_idx_to_str->size()) == idx (/home/jack/HDL/nextpnr-xilinx-sync/common/kernel/idstring.cc:46)
During startup program terminated with signal SIGABRT, Aborted.
(gdb) bt
No stack.

I already rebuilt the chipdb, and I rebuild the Makefiles using

 cmake -DCMAKE_BUILD_TYPE=Debug -DARCH=xilinx -DUSE_IPO=0

And I wonder why I even don't get a stack trace when I run it with gdb. even a breakpoint on main won't work 

(gdb) b main
Breakpoint 1 at 0x3e473f: file /home/jack/HDL/nextpnr-xilinx-sync/xilinx/main.cc, line 89.
(gdb) run
Starting program: /usr/local/bin/nextpnr-xilinx --router router1 --chipdb ../chipdb/xc7k160tffg676-2.bin --xdc enclustra_mercury_kx2.xdc --json enclustra_mercury_kx2.json --write enclustra_mercury_kx2_routed.json --fasm enclustra_mercury_kx2.fasm --verbose --debug
terminate called after throwing an instance of 'nextpnr_xilinx::assertion_failure'
  what():  Assertion failure: int(ctx->idstring_idx_to_str->size()) == idx (/home/jack/HDL/nextpnr-xilinx-sync/common/kernel/idstring.cc:46)
During startup program terminated with signal SIGABRT, Aborted.
(gdb)

Something seriously weird going on, I replace the failed assertion exception with a SIGTRAP, and gdb still does not break. Something seems to be seriously wrong with gdb on Ubuntu 22.04.

I tried the gdb from nixpkgs, same result. Problem is that the error occurs even before reaching main. Did I forget to clean something? I did a make clean and then removed CMakeCache.txt, and then reran cmake.

hansfbaier commented 1 year ago

I used this demo project: https://github.com/openXC7/demo-projects/tree/main/litex-ddr-enclustra-kx2

hansfbaier commented 1 year ago

@mmicko As it turns out, make install does not install bbasm, so all the time I have been using bbasm from my snap, which might be incompatible. Unfortunately I installed the supplied bbasm from the build in /usr/local/bin and I still get the same error:


[07:17:45] /devel/HDL/kintex-reveng/demo-projects/litex-ddr-enclustra-kx2 main|+6…50⚑3+7313-5142$ which bbasm
/usr/local/bin/bbasm
[07:17:55] /devel/HDL/kintex-reveng/demo-projects/litex-ddr-enclustra-kx2 main|+6…50⚑3+7313-5142$ rm ../chipdb/xc7k325tffg676-1.bin
[07:18:07] /devel/HDL/kintex-reveng/demo-projects/litex-ddr-enclustra-kx2 main|+6…50⚑3+7313-5142$ make
pypy3 /snap/openxc7/current/opt/nextpnr-xilinx/python/bbaexport.py --device xc7k160tffg676-2 --bba xc7k160tffg676-2.bba
Exporting tile and site type data...
Exporting nodes...
Exporting tile and site instances...
bbasm -l xc7k160tffg676-2.bba ../chipdb/xc7k160tffg676-2.bin
rm -f xc7k160tffg676-2.bba
nextpnr-xilinx --router router1 --chipdb ../chipdb/xc7k160tffg676-2.bin --xdc enclustra_mercury_kx2.xdc  --json enclustra_mercury_kx2.json --write enclustra_mercury_kx2_routed.json --fasm enclustra_mercury_kx2.fasm  #--verbose --debug
terminate called after throwing an instance of 'nextpnr_xilinx::assertion_failure'
  what():  Assertion failure: int(ctx->idstring_idx_to_str->size()) == idx (/home/jack/HDL/nextpnr-xilinx-sync/common/kernel/idstring.cc:46)
Aborted (core dumped)
make: *** [Makefile:25: enclustra_mercury_kx2.fasm] Error 134
gatecat commented 1 year ago

That error is usually fixed by regenerating the bba and bin; it's when the IdStrings used to generate the bba don't match the constids.inc baked into nextpnr.

If not then something is probably up with the bba generation

hansfbaier commented 1 year ago

@gatecat Yes, but unfortunately this time, updating bbasm and regenerating the chipdb does not fix it:

pypy3 /snap/openxc7/current/opt/nextpnr-xilinx/python/bbaexport.py --device xc7k160tffg676-2 --bba xc7k160tffg676-2.bba
Exporting tile and site type data...
Exporting nodes...
Exporting tile and site instances...
bbasm -l xc7k160tffg676-2.bba ../chipdb/xc7k160tffg676-2.bin
rm -f xc7k160tffg676-2.bba
nextpnr-xilinx --router router1 --chipdb ../chipdb/xc7k160tffg676-2.bin --xdc enclustra_mercury_kx2.xdc  --json enclustra_mercury_kx2.json --write enclustra_mercury_kx2_routed.json --fasm enclustra_mercury_kx2.fasm  #--verbose --debug
terminate called after throwing an instance of 'nextpnr_xilinx::assertion_failure'
  what():  Assertion failure: int(ctx->idstring_idx_to_str->size()) == idx (/home/jack/HDL/nextpnr-xilinx-sync/common/kernel/idstring.cc:46)
Aborted (core dumped)
make: *** [Makefile:25: enclustra_mercury_kx2.fasm] Error 134

Any ideas of how to debug this? @mmicko Does gdb work for you on this issue? For me it doesn't even break on main.

gatecat commented 1 year ago

is /snap/openxc7/current/opt/nextpnr-xilinx/python/bbaexport.py coming from the new codebase and also using the correct constids.inc?