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gatecat / nextpnr-xilinx

Experimental flows using nextpnr for Xilinx devices
ISC License
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DSP48E1 works on Xilinx 7 series #64

Closed hansfbaier closed 1 year ago

hansfbaier commented 1 year ago

Hi, clocked and cascaded DSPs are now working. I just successfully built and run this as a 128x128 bit multiplier design, outputting a times table over the serial line: https://github.com/Open-XC7/dsp-tests/tree/main/mult-harness

hansfbaier commented 1 year ago

Set this to WIP for a moment. I think I should test some more.

hansfbaier commented 1 year ago

This actually isn't WIP anymore. Successfully builds a LiteX Vexriscv design and Ray tracer on it works now.

hansfbaier commented 1 year ago

Also works nicely building a 128x128 bit multiplier using 64 cascaded DSP blocks (IIRC)

hansfbaier commented 1 year ago

So it is definitely already useable.

hansfbaier commented 1 year ago

But it still uses the old parenting contraints.

hansfbaier commented 1 year ago

I also rebased to current xilinx-upstream, so this might be ready to merge!