gatecat
commented
3 years ago Hi! There's a WIP fuzzer for PCIe in https://github.com/gatecat/prjoxide/tree/master/fuzzers/LIFCL/162-pcie-ipconfig, however, the results aren't pushed because I was seeing some dubious output, for example:
+ "BAR_INDEX_CFG4_A": (
+ bits: [
+ [(frame:16823,bit:0,invert:false,),(frame:20919,bit:0,invert:false,),(frame:25015,bit:0,invert:false,),(frame:29111,bit:0,invert:false,),],
+ [(frame:16823,bit:1,invert:false,),(frame:20919,bit:1,invert:false,),(frame:25015,bit:1,invert:false,),(frame:29111,bit:1,invert:false,),],
+ [(frame:16823,bit:2,invert:false,),(frame:20919,bit:2,invert:false,),(frame:25015,bit:2,invert:false,),(frame:29111,bit:2,invert:false,),],
+ ],
+ ),
+ "BAR_INDEX_CFG4_B": (
+ bits: [
+ [],
+ [],
+ [],
+ ],
+ ),
+ "BAR_INDEX_CFG4_C": (
+ bits: [
+ [],
+ [],
+ [],
+ ],where you can see BAR_INDEX_CFG4_A affects four bits but _B and _C affect none. If you have designs that work in Radiant, that's already useful, as I suspect there's some non-obvious interaction between parameters going on.
teknoman117
I finally got my CrossLink-NX evaluation board (with a LICFL-40-8BG400C) and I put together a PCIe x1 to SMA board (https://github.com/teknoman117/PCIEX1-SMA) which I'm currently waiting on to arrive along with all of the SMA connectors and cables. Hopefully everything will be here by the end of the month.
I hope to be able to get a super simple example with the Lattice IP core working soon after assembling everything (basically just hook a GPIO bridge to the AHB-Lite master). After figuring out if it works at all, I'll try to port litepcie to it.
Either way, I just wanted to reach out to say that if PCIe support hasn't been figured out yet due to a lack of PCIe capable hardware, I will soon be able to run whatever tests you want.