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gatecat / prjoxide

Documenting Lattice's 28nm FPGA parts
ISC License
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Fix 05-clock timing fuzzer #23

Closed mtdudek closed 2 years ago

mtdudek commented 2 years ago

In radiant 3.0 signal cannot drive DCC's CLKI and CE at the same time, even if these are 2 different instances of this primitive. This was solved by moving ctrl signals to r[21:24]. Get_source was broken when DCS where used. DCS calls get_source twice using up 2 extra clock signals. This introduced undefined r[21] and r[22] signals, which were conneced by default to GND_net.

Signed-off-by: Maciej Dudek mdudek@antmicro.com

mtdudek commented 2 years ago

Ping @gatecat

mtdudek commented 2 years ago

@gatecat I think you may be Interested in this PR. It fixes some issues with clock timing fuzzer.

gatecat commented 2 years ago

Sorry for the delay there