geerlingguy
commented
8 months ago Just plopped this board on my Compute Module 4 IO Board, and it seems to do some sort of boot process, arriving at a flashing green LED (two flashes, then 1 second break, repeating).
The network LEDs light up too, but I don't see a new device on the network. No HDMI output, and I'm not 100% sure if the GPIO pinout is the same as Pi CM4, so I don't want to plug in UART yet...
I tried accessing the 'Get Started' docs page listed on the side of the box (http://milkv.io/docs/mars-cm), but that page is currently giving a 404 Page Not Found.
I've opened up an issue on the MilkV Community Forum: Mars CM - Getting Started guide missing?.
It would be great if this JH7110-based board could run as a drop-in replacement of the Compute Module 4... we'll see!
christiancelona
eshattow
ThomasKaiser
rhinot
tumetuoppi
taspenwall
carbonfix
platima
mr-c
Basic information
Linux/system information
Benchmark results
CPU
Power
stress-ng --matrix 0): 3.8 Wtop500HPL benchmark: 3.6 WDisk
Built-in 16 GB eMMC Module
2TB Kioxia XG8 NVMe SSD (via PCIe Gen 2 x1 interface)
curl https://raw.githubusercontent.com/geerlingguy/pi-cluster/master/benchmarks/disk-benchmark.sh | sudo bashRun benchmark on any attached storage device (e.g. eMMC, microSD, NVMe, SATA) and add results under an additional heading. Download the script with
curl -o disk-benchmark.sh [URL_HERE]and runsudo DEVICE_UNDER_TEST=/dev/sda DEVICE_MOUNT_PATH=/mnt/sda1 ./disk-benchmark.sh(assuming the device issda).Also consider running PiBenchmarks.com script.
Network
iperf3results:1 Gbps Ethernet (built-in)
iperf3 -c $SERVER_IP: 920 Mbpsiperf3 --reverse -c $SERVER_IP: 879 Mbpsiperf3 --bidir -c $SERVER_IP: 941 Mbps up, 258 Mbps downWiFi (built-in)
iperf3 -c $SERVER_IP: TODO Mbpsiperf3 --reverse -c $SERVER_IP: TODO Mbpsiperf3 --bidir -c $SERVER_IP: TODO Mbps up, TODO Mbps downGPU
Memory
tinymembenchresults:Click to expand memory benchmark result
``` tinymembench v0.4.10 (simple benchmark for memory throughput and latency) ========================================================================== == Memory bandwidth tests == == == == Note 1: 1MB = 1000000 bytes == == Note 2: Results for 'copy' tests show how many bytes can be == == copied per second (adding together read and writen == == bytes would have provided twice higher numbers) == == Note 3: 2-pass copy means that we are using a small temporary buffer == == to first fetch data into it, and only then write it to the == == destination (source -> L1 cache, L1 cache -> destination) == == Note 4: If sample standard deviation exceeds 0.1%, it is shown in == == brackets == ========================================================================== C copy backwards : 993.0 MB/s (0.7%) C copy backwards (32 byte blocks) : 991.7 MB/s C copy backwards (64 byte blocks) : 991.7 MB/s C copy : 1002.3 MB/s C copy prefetched (32 bytes step) : 1001.8 MB/s (0.4%) C copy prefetched (64 bytes step) : 1003.6 MB/s (0.4%) C 2-pass copy : 829.9 MB/s C 2-pass copy prefetched (32 bytes step) : 833.9 MB/s C 2-pass copy prefetched (64 bytes step) : 832.6 MB/s (0.1%) C fill : 868.7 MB/s (0.2%) C fill (shuffle within 16 byte blocks) : 864.9 MB/s C fill (shuffle within 32 byte blocks) : 868.8 MB/s (0.3%) C fill (shuffle within 64 byte blocks) : 876.2 MB/s (0.4%) --- standard memcpy : 1004.5 MB/s standard memset : 884.3 MB/s (0.6%) ========================================================================== == Memory latency test == == == == Average time is measured for random memory accesses in the buffers == == of different sizes. The larger is the buffer, the more significant == == are relative contributions of TLB, L1/L2 cache misses and SDRAM == == accesses. For extremely large buffer sizes we are expecting to see == == page table walk with several requests to SDRAM for almost every == == memory access (though 64MiB is not nearly large enough to experience == == this effect to its fullest). == == == == Note 1: All the numbers are representing extra time, which needs to == == be added to L1 cache latency. The cycle timings for L1 cache == == latency can be usually found in the processor documentation. == == Note 2: Dual random read means that we are simultaneously performing == == two independent memory accesses at a time. In the case if == == the memory subsystem can't handle multiple outstanding == == requests, dual random read has the same timings as two == == single reads performed one after another. == ========================================================================== block size : single random read / dual random read 1024 : 0.0 ns / 0.0 ns 2048 : 0.0 ns / 0.0 ns 4096 : 0.0 ns / 0.0 ns 8192 : 0.0 ns / 0.0 ns 16384 : 0.0 ns / 0.0 ns 32768 : 0.0 ns / 0.0 ns 65536 : 5.4 ns / 10.5 ns 131072 : 8.1 ns / 15.8 ns 262144 : 9.5 ns / 18.6 ns 524288 : 15.4 ns / 28.6 ns 1048576 : 16.0 ns / 30.6 ns 2097152 : 21.9 ns / 38.5 ns 4194304 : 84.8 ns / 166.5 ns 8388608 : 122.4 ns / 242.6 ns 16777216 : 143.7 ns / 285.6 ns 33554432 : 157.2 ns / 313.1 ns 67108864 : 167.7 ns / 334.6 ns ```Phoronix Test Suite
Results from pi-general-benchmark.sh:
sbc-benchresults