schoolpost
commented
17 hours ago Thanks for all the thorough performance numbers, can you confirm CM5 uses the D0 variant of the BCM2712?
Open geerlingguy opened 18 hours ago
schoolpost
commented
17 hours ago Thanks for all the thorough performance numbers, can you confirm CM5 uses the D0 variant of the BCM2712?
geerlingguy
commented
16 hours ago @schoolpost - All the ones I've seen are D0, yes.
geerlingguy
commented
7 hours ago Home Assistant Yellow is also a drop-in upgrade, in addition to all the Compute Module carrier boards I mentioned in my video: https://www.youtube.com/watch?v=X4blR5Ua3S0
Basic information
All tests were run on the 4GB board, except as noted. Some tests scale with RAM.
Linux/system information
Benchmark results
CPU
Power
stress-ng --matrix 0): 8.5 Wtop500HPL benchmark: 9.4 W (10 W on 8GB)Disk
Pinedrive 256GB 2242 NVMe SSD at PCIe Gen 3
Built-in eMMC (32GB)
Network
iperf3results:Built-in 1 Gbps Ethernet (BCM54210PE)
iperf3 -c $SERVER_IP: 938 Mbpsiperf3 -c $SERVER_IP --reverse: 884 Mbpsiperf3 -c $SERVER_IP --bidir: 931 Mbps up, 663 Mbps downWiFi (built-in PCB antenna)
iperf3 -c $SERVER_IP: 249 Mbpsiperf3 -c $SERVER_IP --reverse: 240 Mbpsiperf3 -c $SERVER_IP --bidir: 133 Mbps up, 96.6 Mbps downWiFi (external antenna)
iperf3 -c $SERVER_IP: 250 Mbpsiperf3 -c $SERVER_IP --reverse: 245 Mbpsiperf3 -c $SERVER_IP --bidir: 113 Mbps up, 120 Mbps down(Measured for optimal antenna orientation with
sudo apt install wavemon, andwavemon)GPU
glmark2
glmark2-es2/glmark2-es2-waylandresults:Note: This benchmark requires an active display on the device. Not all devices may be able to run
glmark2-es2, so in that case, make a note and move on!Ollama
ollamaLLM model inference results:Power consumption was a steady 9.3W during inference.
Memory
tinymembenchresults:Click to expand memory benchmark result
``` tinymembench v0.4.10 (simple benchmark for memory throughput and latency) ========================================================================== == Memory bandwidth tests == == == == Note 1: 1MB = 1000000 bytes == == Note 2: Results for 'copy' tests show how many bytes can be == == copied per second (adding together read and writen == == bytes would have provided twice higher numbers) == == Note 3: 2-pass copy means that we are using a small temporary buffer == == to first fetch data into it, and only then write it to the == == destination (source -> L1 cache, L1 cache -> destination) == == Note 4: If sample standard deviation exceeds 0.1%, it is shown in == == brackets == ========================================================================== C copy backwards : 5303.7 MB/s (0.2%) C copy backwards (32 byte blocks) : 5333.1 MB/s (0.2%) C copy backwards (64 byte blocks) : 5328.4 MB/s C copy : 6061.3 MB/s (0.1%) C copy prefetched (32 bytes step) : 6031.9 MB/s C copy prefetched (64 bytes step) : 6036.9 MB/s C 2-pass copy : 5433.6 MB/s C 2-pass copy prefetched (32 bytes step) : 6003.8 MB/s (0.1%) C 2-pass copy prefetched (64 bytes step) : 5996.6 MB/s C fill : 12660.7 MB/s (0.2%) C fill (shuffle within 16 byte blocks) : 12630.7 MB/s C fill (shuffle within 32 byte blocks) : 12628.8 MB/s C fill (shuffle within 64 byte blocks) : 12642.2 MB/s NEON 64x2 COPY : 5996.0 MB/s (1.0%) NEON 64x2x4 COPY : 5996.6 MB/s NEON 64x1x4_x2 COPY : 6006.0 MB/s NEON 64x2 COPY prefetch x2 : 5517.6 MB/s NEON 64x2x4 COPY prefetch x1 : 5587.1 MB/s NEON 64x2 COPY prefetch x1 : 5494.3 MB/s NEON 64x2x4 COPY prefetch x1 : 5596.0 MB/s (0.6%) --- standard memcpy : 6012.7 MB/s standard memset : 12646.0 MB/s (0.3%) --- NEON LDP/STP copy : 6012.5 MB/s (0.1%) NEON LDP/STP copy pldl2strm (32 bytes step) : 6014.6 MB/s (0.2%) NEON LDP/STP copy pldl2strm (64 bytes step) : 6013.5 MB/s NEON LDP/STP copy pldl1keep (32 bytes step) : 5997.7 MB/s NEON LDP/STP copy pldl1keep (64 bytes step) : 5995.9 MB/s NEON LD1/ST1 copy : 6002.0 MB/s NEON STP fill : 12634.8 MB/s (0.8%) NEON STNP fill : 12640.2 MB/s (0.7%) ARM LDP/STP copy : 6011.4 MB/s (0.6%) ARM STP fill : 12403.9 MB/s (0.4%) ARM STNP fill : 12408.2 MB/s (0.2%) ========================================================================== == Framebuffer read tests. == == == == Many ARM devices use a part of the system memory as the framebuffer, == == typically mapped as uncached but with write-combining enabled. == == Writes to such framebuffers are quite fast, but reads are much == == slower and very sensitive to the alignment and the selection of == == CPU instructions which are used for accessing memory. == == == == Many x86 systems allocate the framebuffer in the GPU memory, == == accessible for the CPU via a relatively slow PCI-E bus. Moreover, == == PCI-E is asymmetric and handles reads a lot worse than writes. == == == == If uncached framebuffer reads are reasonably fast (at least 100 MB/s == == or preferably >300 MB/s), then using the shadow framebuffer layer == == is not necessary in Xorg DDX drivers, resulting in a nice overall == == performance improvement. For example, the xf86-video-fbturbo DDX == == uses this trick. == ========================================================================== NEON LDP/STP copy (from framebuffer) : 1939.3 MB/s (0.7%) NEON LDP/STP 2-pass copy (from framebuffer) : 1737.0 MB/s (0.2%) NEON LD1/ST1 copy (from framebuffer) : 1945.3 MB/s (0.2%) NEON LD1/ST1 2-pass copy (from framebuffer) : 1736.1 MB/s ARM LDP/STP copy (from framebuffer) : 1894.0 MB/s (0.1%) ARM LDP/STP 2-pass copy (from framebuffer) : 1732.5 MB/s (0.1%) ========================================================================== == Memory latency test == == == == Average time is measured for random memory accesses in the buffers == == of different sizes. The larger is the buffer, the more significant == == are relative contributions of TLB, L1/L2 cache misses and SDRAM == == accesses. For extremely large buffer sizes we are expecting to see == == page table walk with several requests to SDRAM for almost every == == memory access (though 64MiB is not nearly large enough to experience == == this effect to its fullest). == == == == Note 1: All the numbers are representing extra time, which needs to == == be added to L1 cache latency. The cycle timings for L1 cache == == latency can be usually found in the processor documentation. == == Note 2: Dual random read means that we are simultaneously performing == == two independent memory accesses at a time. In the case if == == the memory subsystem can't handle multiple outstanding == == requests, dual random read has the same timings as two == == single reads performed one after another. == ========================================================================== block size : single random read / dual random read 1024 : 0.0 ns / 0.0 ns 2048 : 0.0 ns / 0.0 ns 4096 : 0.0 ns / 0.0 ns 8192 : 0.0 ns / 0.0 ns 16384 : 0.0 ns / 0.0 ns 32768 : 0.0 ns / 0.0 ns 65536 : 0.0 ns / 0.0 ns 131072 : 1.1 ns / 1.5 ns 262144 : 1.6 ns / 2.0 ns 524288 : 2.3 ns / 2.9 ns 1048576 : 8.3 ns / 11.3 ns 2097152 : 15.1 ns / 19.0 ns 4194304 : 51.5 ns / 77.4 ns 8388608 : 79.8 ns / 108.0 ns 16777216 : 94.9 ns / 119.5 ns 33554432 : 104.4 ns / 126.1 ns 67108864 : 110.0 ns / 130.3 ns ```sbc-benchresultsRun sbc-bench and paste a link to the results here: https://0x0.st/XRKg.txt
Phoronix Test Suite
Results from pi-general-benchmark.sh:
Other benchmarks