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gem5
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gem5
The official repository for the gem5 computer-system architecture simulator.
http://www.gem5.org
BSD 3-Clause "New" or "Revised" License
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mem-ruby: Fix conflict between 117 and 1084
#1813
giactra
opened
4 hours ago
1
arch-arm: Print the ESR_ELx register when generating a fault
#1812
giactra
opened
6 hours ago
0
arch-x86, sim-se: move mmap end downward in case of large stacks
#1810
nmosier
opened
18 hours ago
0
x86 se workload crashes on large stack allocations
#1809
nmosier
opened
18 hours ago
0
sim-se, arch-x86: implement/ignore sched_get* syscalls
#1808
nmosier
opened
20 hours ago
0
NVM config script (sweep_hybrid.py) throws fatal error when running.
#1805
mostafadx
opened
1 day ago
0
arch-arm: Fix bug in VQRSHL.
#1804
giactra
closed
6 hours ago
0
tests: add non KVM CPU type switch tests
#1801
erin-le
opened
4 days ago
0
fix delayed execution bug when using classic cache model
#1797
2channelkrt
opened
5 days ago
0
tests: modify gem5/learning-gem5 ref file to fix failure
#1795
erin-le
opened
5 days ago
0
util: Adding TargetNamedBreakpoint class for gdb.
#1794
mahyarsamani
opened
5 days ago
1
base: Fix failing compiler tests
#1793
ivanaamit
closed
3 days ago
0
arch-arm: Make FEAT_SME visible in userspace for SE mode
#1792
giactra
closed
5 days ago
0
python: modify comment for ExitEvent.WORKEND
#1790
erin-le
closed
1 week ago
0
arch-arm,misc: Fix build errors
#1789
BobbyRBruce
closed
1 week ago
0
Remove cyclic dependency of SimObjects and probes
#1787
odanrc
opened
1 week ago
3
Add a unit test for bloom filters
#1786
odanrc
opened
1 week ago
4
misc: Fix scons tags
#1785
odanrc
opened
1 week ago
1
Kconfig file Permission Denied
#1784
GroundbreakerLhy
closed
1 week ago
0
Documentation for default exit event behavior is wrong
#1783
powerjg
closed
1 week ago
0
arch-riscv: fix reg dep autoref on vslide with vcpy micro
#1782
saul44203
closed
1 week ago
0
tests: update gpu weekly test to test mis hip instead of fw hip
#1780
Harshil2107
closed
1 week ago
5
Update exit event to send in integer from simulation to host
#1779
Harshil2107
opened
1 week ago
2
Getting warn message of address is outside of physical memory, stopping fetch in O3 riscv core
#1778
faridsamandi
opened
1 week ago
0
mem,ruby: Adding SimObject name to SLICC errors.
#1775
mahyarsamani
closed
1 week ago
0
X86 LAPIC Local Timer still alarm after masked
#1771
attr0
opened
2 weeks ago
0
tests: add x86-ubuntu-run-with-kvm-no-perf to tests
#1770
erin-le
opened
2 weeks ago
0
Reverting L1 Bentries and L1, L2, L3 Bassoc back to 32 from 64.
#1769
shreyamukh
opened
2 weeks ago
4
arch-riscv: Use getValidAddr to get zero-extend address in RV32 mode
#1768
rogerchang23424
closed
17 hours ago
2
arch-riscv: Add support for Zfa extension
#1767
5265325
opened
2 weeks ago
0
stdlib: fix LoopPoint module not getting relative counts
#1766
studyztp
opened
2 weeks ago
1
arch-riscv: Fix incomplete copy-constructor
#1765
zzz00yx
closed
1 week ago
0
misc: Fix typo in README.md
#1763
SimonLammer
closed
2 weeks ago
2
base: Introduce registerExtraLog() in Logger
#1762
yp155136
closed
2 weeks ago
1
arch-riscv: Implement Zcmt
#1761
rogerchang23424
opened
2 weeks ago
0
arch-riscv: fix vrgather pin count
#1759
saul44203
closed
2 weeks ago
0
arch, cpu: Add generic getValidAddr to correct exetrace symbol table
#1758
rogerchang23424
closed
2 weeks ago
0
arch-riscv: sign-extend the PC when enter/leave trap handler
#1756
rogerchang23424
closed
2 weeks ago
0
configs: Update legacy RISC-V FS Linux script
#1753
tommarin
closed
2 weeks ago
0
arch-arm: Cache a pointer to previously matched TLB entry
#1752
giactra
closed
3 weeks ago
0
arch-arm: Use the cached release object instead of HaveExt
#1751
giactra
closed
3 weeks ago
0
misc: update RELEASE-NOTES.md for simInsts and simOps
#1750
erin-le
closed
2 weeks ago
0
misc: bump pre-commit from 3.8.0 to 4.0.1
#1749
dependabot[bot]
closed
2 weeks ago
0
misc: bump mypy from 1.11.2 to 1.13.0
#1748
dependabot[bot]
closed
2 weeks ago
0
misc: bump tqdm from 4.66.5 to 4.66.6
#1747
dependabot[bot]
closed
3 weeks ago
0
mem-ruby: Fix two NetDest locals using default constructor
#1746
abmerop
closed
3 weeks ago
0
Add Python interface to get port actual name
#1744
handsomeliu-google
closed
3 weeks ago
0
stdlib: Add interface to set binary in fs mode
#1743
powerjg
closed
2 weeks ago
3
arch-riscv: Implement a unified L2 TLB
#1741
ncppd
opened
3 weeks ago
9
arch-arm: Do not compute purifyTaggedAddr in checkPermissions
#1739
giactra
closed
3 weeks ago
0
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