Sail -> ArchC

[martinberger]

Two questions:

1. Is there a description of the ArchC grammar used in gensim or just the ANTLER parser?

2. Do you know if there is a tool that translates Sail into ArchC, or if somebody is working on this?

[tspink]

Hi Martin,

1. The only description is the ANTLR grammar file
2. There is no tool, and nobody is currently working on it. I think the best approach would actually be a SAIL frontend to GenSim, rather than a transpiler.

Tom

[martinberger]

Hello Tom, I agree that in the long term a Sail frontend would be best. But I can imagine that a Sail -> ArchC transpiler might be a faster way to bootstrap the whole process. Such a transpiler could also be used as a testing oracle during development of a Sail frontend to gensim. What do you think would be a faster course of action?

[tspink]

Hi Martin,

I was recently looking at the Sail description for RISC-V, but there appears to be fundamental difference in the fundamental approach used.

From what I can see, the Sail description implements a simulator for the RISC-V architecture, by defining everything that the simulator needs to operate, e.g. the fetch/decode/execute loop, etc.

GenSim is a simulator description language, and as such doesn't have the concept of anything other than instruction descriptions and instruction behaviours. Since there doesn't appear to be a clear separation in Sail of "how an instruction is decoded", and "how an instruction is executed", or seemingly a way to identify which parts of a Sail program correspond to instruction decodings, or their behaviours, I think there is a serious issue that needs to be addressed.

GenSim requires information on how to decode an instruction, and information on how to execute an instruction, not a "whole simulator" definition, because GenSim itself generates the simulator modules.

Does this make sense? Perhaps I'm misunderstanding something about the Sail description, but the problem I see is how to identify which parts actually says, "this is how to decode an instruction", so that the corresponding part of gensim can be told "this is how to decode an instruction".

[martinberger]

That's a good point. One way to address this would be only to accept a subset of Sail where execute and decode are treated as keywords. OTOH, they do generate C and Ocaml simulators already, I think automatically.

[martinberger]

That's a good point. One way to address this would be only to accept a subset of Sail where execute and decode are treated as keywords. OTOH, they do generate C and Ocaml simulators already, I think automatically.

Maybe it's necessary to write a custom translator from Sail to ArchC for each Sail program, which separates instruction description and instruction behaviour. Not ideal, I know.

[tspink]

Indeed, or perhaps if there was a "glue" file, which told the translator where the root of the instruction patterns were (if there is such a thing), that may help.

[martinberger]

Yes, that would be even easier.

[martinberger]

This discussion might be of interest: https://github.com/rems-project/sail/issues/76