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geotrieu
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ezRISC
Simple RISC Computer built in Verilog
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is this project open source?
#29
BluBloos
opened
1 year ago
1
added an instruction counter
#28
geotrieu
closed
2 years ago
0
Fixed bugs, Added some Control Signals to Input
#27
geotrieu
closed
2 years ago
0
done some stuff
#26
geotrieu
closed
2 years ago
0
setup memory for phase 4
#25
Carib08
closed
2 years ago
0
completed implementation and testing of control unit/phase 3
#24
Carib08
closed
2 years ago
0
more work on implementing control unit
#23
Carib08
closed
2 years ago
0
Dev gtrieu
#22
geotrieu
closed
2 years ago
0
added all states other then nop and halt
#21
Carib08
closed
2 years ago
0
Dev mgarv
#20
Carib08
closed
2 years ago
0
Add branch and jump testbenches and extra logic
#19
geotrieu
closed
2 years ago
0
Added Select and Encode Documentation
#18
geotrieu
closed
2 years ago
0
Dev mgarv
#17
Carib08
closed
2 years ago
0
Added Store Testbench
#16
geotrieu
closed
2 years ago
0
Dev mgarv
#15
Carib08
closed
2 years ago
0
Added Inport and Outport functionality
#14
geotrieu
closed
2 years ago
0
Added select encode logic, R0 Extension, and preliminary Con FF Logic
#13
geotrieu
closed
2 years ago
0
Dev mgarv
#12
Carib08
closed
2 years ago
0
Fixed issue with rotation not masking hi bits
#11
Carib08
closed
2 years ago
0
More in-depth Documentation
#10
geotrieu
closed
2 years ago
0
Dev mgarv
#9
Carib08
closed
2 years ago
0
Added Half of the Testbench Cases for Datapath
#8
geotrieu
closed
2 years ago
0
Added datapath design architecture
#7
geotrieu
closed
2 years ago
0
added functionality to return remainder in upper 32 bits of Z reg
#6
Carib08
closed
2 years ago
0
Added PC Increment Functionality and Refactored some Code
#5
geotrieu
closed
2 years ago
0
Merge dev-gtrieu to master
#4
geotrieu
closed
2 years ago
0
Implemented non restoring divider for alu
#3
Carib08
closed
2 years ago
0
forgot to add files oop
#2
Carib08
closed
2 years ago
0
Dev mgarv
#1
Carib08
closed
2 years ago
0