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gergoerdi / clash-spaceinvaders

Intel 8080-based Space Invaders arcade machine implemented on an FPGA, written in CLaSH
MIT License
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Implement READY / WAIT pins #3

Open gergoerdi opened 5 years ago

gergoerdi commented 5 years ago

http://www.hartetechnologies.com/manuals/Intel/Intel%208080%20System%20Manual.pdf

http://www.nj7p.info/Manuals/PDFs/Intel/9800153B.pdf

Memory pulls READY low to make CPU wait, CPU acknowledges it by pulling WAIT high. When READY is pulled high again, the CPU exits waiting stage:

Once the processor has sent an address to memory, there is an opportunity for the memory to request a WAIT. This it does by pulling the processor's READY line low, prior to the "Ready set-up" interval (tRS) which occurs during the (/)2 pulse within state T2 or TW. As long as the REAOY line remains low, the processor will idle, giving the memory time to respond to the addressed data request. Refer to Figure 2-5. The processor responds to a wait request by entering an alternative state (TW) at the end of T2, rather than proceed ing directly to the T 3 state. Entry into the TW state is indicated by a WAIT signal from the processor, acknowledging the memory's request. A low-to-high transition on the WAIT line is triggered by the rising edge of the (/)1 clock and occurs within a brief delay (tOC) of the actual entry into the TW state. A wait period may be of indefinite duration. The processor remains in the waiting condition until its READY line again goes high. A READY indication must precede the failing edge of the (/)2 clock by a specified interval (tRS), in order to guarantee an exit from the TW state. The cycle may then proceed, beginning with the rising edge of the next (/)1 clock. A WAIT interval will therefore consist of an integral number of TW states and will always be a multiple of the clock period.