This touched a lot of our code, so it may be hard to review. Except for the monotonic impl, it should be all mechanical changes without change in behavior. It works on my device š
The monotonic implementation had to be re-done completely.
With the new trait, things become simpler, but we cannot use TIM6 anymore because it doesn't have a capture/compare register. Instead, I used LPTIM, which has the advantage that it could be used to schedule tasks while in a low power state, which means that we could further optimize by putting the microcontroller in one of those low-power states when waiting for a scheduled task (but when not yet in standby).
LPTIM is configured to use LSE (the external 32.768 kHz crystal) as clock source, making it independent of the core clock. (LSE always works, since we need it for the RTC.)
I replaced the custom Instant/Delay implementation with fugit.
The 16-bit timer is now software-extended to 32 bits using an overflow counter, meaning that we can now schedule tasks more than 4s into the future (and we have 32 kHz tick resolution instead of 8 kHz). This has two tradeoffs: There are additional interrupts (the overflow, but that happens only every 2s) and RTIC cannot disable the timer when no task is scheduled. However, that doesn't matter to us, because either we have scheduled tasks, or we're in standby.
Resources are now split into shared and local resources. I moved all resources that we only use in a single task to the local resources.
This touched a lot of our code, so it may be hard to review. Except for the monotonic impl, it should be all mechanical changes without change in behavior. It works on my device š
Some relevant changes: