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gfx-rs / wgpu

A cross-platform, safe, pure-Rust graphics API.
https://wgpu.rs
Apache License 2.0
11.46k stars 855 forks source link

STATUS_ACCESS_VIOLATION when running wgpu::Surface::configure() #5879

Open myth0genesis opened 3 days ago

myth0genesis commented 3 days ago

After having compiled and run the program successfully several times, without changing a single line of code, I suddenly began receiving an

error: process didn't exit successfully: `target\debug\wgpu_shader_output.exe` (exit code: 0xc0000005, STATUS_ACCESS_VIOLATION)

error.

Source files: lib.rs:

use std::sync::Arc;

use pollster::FutureExt;
use wgpu::{
    Adapter,
    Device,
    Instance,
    PresentMode,
    Queue,
    Surface,
    SurfaceCapabilities,
};
use winit::application::ApplicationHandler;
use winit::dpi::PhysicalSize;
use winit::event::WindowEvent;
use winit::event_loop::{ActiveEventLoop, EventLoop};
use winit::window::{Window, WindowId};

pub async fn run() {
    let event_loop = EventLoop::new().unwrap();

    let mut window_state = StateApplication::new();
    let _ = event_loop.run_app(&mut window_state);
}

struct StateApplication<'a> {
    state: Option<State<'a>>,
}

impl<'a> StateApplication<'a> {
    pub fn new() -> Self {
        Self {
            state: None,
        }
    }
}

impl<'a> ApplicationHandler for StateApplication<'a> {
    fn resumed(&mut self, event_loop: &ActiveEventLoop) {
        let window = event_loop.create_window(Window::default_attributes().with_title("Hello!")).unwrap();
        self.state = Some(State::new(window));
    }

    fn window_event(&mut self, event_loop: &ActiveEventLoop, window_id: WindowId, event: WindowEvent) {
        let window = self.state.as_ref().unwrap().window();

        if window.id() == window_id {
            let state_mut = self.state.as_mut().unwrap();
            match event {
                WindowEvent::CloseRequested => {
                    event_loop.exit();
                }
                WindowEvent::Resized(physical_size) => {
                    state_mut.resize(physical_size);
                }
                WindowEvent::RedrawRequested => {
                    state_mut.render().unwrap();
                }
                _ => {}
            }
        }
    }

    fn about_to_wait(&mut self, _event_loop: &ActiveEventLoop) {
        let window = self.state.as_ref().unwrap().window();
        window.request_redraw();
    }
}

struct State<'a> {
    surface: Surface<'a>,
    device: Device,
    queue: Queue,
    config: wgpu::SurfaceConfiguration,

    size: PhysicalSize<u32>,
    window: Arc<Window>,
}

impl<'a> State<'a> {
    pub fn new (window: Window) -> Self {
        let window_arc = Arc::new(window);
        let size = window_arc.inner_size();
        let instance = Self::create_gpu_instance();
        let surface = instance.create_surface(window_arc.clone()).unwrap();
        let adapter = Self::create_adapter(instance, &surface);
        let (device, queue) = Self::create_device(&adapter);
        let surface_caps = surface.get_capabilities(&adapter);
        let config = Self::create_surface_config(size, surface_caps);
        surface.configure(&device, &config);

        Self {
            surface,
            device,
            queue,
            config,
            size,
            window: window_arc,
        }
    }

    fn create_surface_config(size: PhysicalSize<u32>, capabilities: SurfaceCapabilities) -> wgpu::SurfaceConfiguration {
        let surface_format = capabilities.formats.iter()
            .find(|f| f.is_srgb())
            .copied()
            .unwrap_or(capabilities.formats[0]);

        wgpu::SurfaceConfiguration {
            usage: wgpu::TextureUsages::RENDER_ATTACHMENT,
            format: surface_format,
            width: size.width,
            height: size.height,
            present_mode: PresentMode::Fifo,
            alpha_mode: capabilities.alpha_modes[0],
            view_formats: vec![],
            desired_maximum_frame_latency: 2,
        }
    }

    fn create_device(adapter: &Adapter) -> (Device, Queue) {
        adapter.request_device(
            &wgpu::DeviceDescriptor {
                required_features: wgpu::Features::empty(),
                required_limits: wgpu::Limits::default(),
                label: None
            },
            None
        ).block_on().unwrap()
    }

    fn create_adapter(instance: Instance, surface: &Surface) -> Adapter {
        instance.request_adapter(
            &wgpu::RequestAdapterOptions {
                power_preference: wgpu::PowerPreference::default(),
                compatible_surface: Some(surface),
                force_fallback_adapter: false,
            }
        ).block_on().unwrap()
    }

    fn create_gpu_instance() -> Instance {
        Instance::new(wgpu::InstanceDescriptor {
            backends: wgpu::Backends::PRIMARY,
            ..Default::default()
        })
    }

    pub fn resize(&mut self, new_size: PhysicalSize<u32>) {
        self.size = new_size;

        self.config.width = new_size.width;
        self.config.height = new_size.height;

        self.surface.configure(&self.device, &self.config);

        println!("Resized to {:?} from state!", new_size);
    }

    pub fn render(&mut self) -> Result<(), wgpu::SurfaceError> {
        let output = self.surface.get_current_texture().unwrap();
        let view = output.texture.create_view(&wgpu::TextureViewDescriptor::default());

        let mut encoder = self.device.create_command_encoder(&wgpu::CommandEncoderDescriptor {
            label: Some("Render Encoder"),
        });

        {
            let _render_pass = encoder.begin_render_pass(&wgpu::RenderPassDescriptor {
                label: Some("Render Pass"),
                color_attachments: &[Some(wgpu::RenderPassColorAttachment {
                    view: &view,
                    resolve_target: None,
                    ops: wgpu::Operations {
                        load: wgpu::LoadOp::Clear(wgpu::Color {
                            r: 1.0,
                            g: 0.2,
                            b: 0.3,
                            a: 1.0,
                        }),
                        store: wgpu::StoreOp::Store,
                    }
                })],
                depth_stencil_attachment: None,
                occlusion_query_set: None,
                timestamp_writes: None,
            });
        }

        self.queue.submit(std::iter::once(encoder.finish()));
        output.present();

        Ok(())
    }

    pub fn window(&self) -> &Window {
        &self.window
    }
}

main.rs:

use wgpu_shader_output::run;

fn main() {
    pollster::block_on(run());
}

Cargo.toml:

[package]
name = "wgpu_shader_output"
version = "0.1.0"
edition = "2021"

[dependencies]
pollster = "0.3.0"
wgpu = "0.20.0"
winit = "0.30.0"

Expected behavior: A window should show up on-screen with a solid red interior when compiling and running the above project.

Observed behavior: When running, the program exits with an

error: process didn't exit successfully: `target\debug\wgpu_shader_output.exe` (exit code: 0xc0000005, STATUS_ACCESS_VIOLATION)

error.

Extra information: When debugging, the failure occurs at any line containing

surface.configure();

Here's is the output at the point of failure:

; Symbol: D3D12TranslateCreateDevice
; Source: unknown
7FFD320405E0: 48 8B C4                   movq   %rsp, %rax
7FFD320405E3: 56                         pushq  %rsi
7FFD320405E4: 57                         pushq  %rdi
7FFD320405E5: 41 56                      pushq  %r14
7FFD320405E7: 48 83 EC 70                subq   $0x70, %rsp
7FFD320405EB: 48 C7 40 98 FE FF FF FF    movq   $-0x2, -0x68(%rax)
7FFD320405F3: 48 89 58 18                movq   %rbx, 0x18(%rax)
7FFD320405F7: 4D 8B F0                   movq   %r8, %r14
7FFD320405FA: 48 8B F2                   movq   %rdx, %rsi
7FFD320405FD: 33 FF                      xorl   %edi, %edi
7FFD320405FF: 85 C9                      testl  %ecx, %ecx
7FFD32040601: 40 0F 95 C7                setne  %dil
7FFD32040605: 4C 8D 0D D4 51 4F 00       leaq   0x4f51d4(%rip), %r9
7FFD3204060C: 45 33 C0                   xorl   %r8d, %r8d
7FFD3204060F: 48 8D 15 7A 3A 00 00       leaq   0x3a7a(%rip), %rdx  ; <+15024>
7FFD32040616: 48 8D 0D BB 51 4F 00       leaq   0x4f51bb(%rip), %rcx
7FFD3204061D: 48 FF 15 5C AA 3A 00       callq  *0x3aaa5c(%rip)
7FFD32040624: 0F 1F 44 00 00             nopl   (%rax,%rax)
7FFD32040629: 85 C0                      testl  %eax, %eax
7FFD3204062B: 74 39                      je     0x7ffd32040666  ; <+134>
7FFD3204062D: 48 8B 05 AC 51 4F 00       movq   0x4f51ac(%rip), %rax
7FFD32040634: 48 8B 00                   movq   (%rax), %rax
7FFD32040637: 48 85 C0                   testq  %rax, %rax
7FFD3204063A: 74 2A                      je     0x7ffd32040666  ; <+134>
7FFD3204063C: 49 BA 70 BB D5 1A EB 1F >  movabsq $-0x2bc2e014e52a4490, %r10  ; imm = 0xD43D1FEB1AD5BB70 
7FFD32040646: 48 8D 94 24 98 00 00 00    leaq   0x98(%rsp), %rdx
7FFD3204064E: 48 8D 0D 73 C1 3B 00       leaq   0x3bc173(%rip), %rcx
7FFD32040655: FF 15 B5 B0 3A 00          callq  *0x3ab0b5(%rip)
7FFD3204065B: 85 C0                      testl  %eax, %eax
7FFD3204065D: 74 07                      je     0x7ffd32040666  ; <+134>
7FFD3204065F: 23 BC 24 98 00 00 00       andl   0x98(%rsp), %edi
7FFD32040666: 4C 8D 0D 73 51 4F 00       leaq   0x4f5173(%rip), %r9
7FFD3204066D: 45 33 C0                   xorl   %r8d, %r8d
7FFD32040670: 48 8D 15 19 3A 00 00       leaq   0x3a19(%rip), %rdx  ; <+15024>
7FFD32040677: 48 8D 0D 5A 51 4F 00       leaq   0x4f515a(%rip), %rcx
7FFD3204067E: 48 FF 15 FB A9 3A 00       callq  *0x3aa9fb(%rip)
7FFD32040685: 0F 1F 44 00 00             nopl   (%rax,%rax)
7FFD3204068A: 85 C0                      testl  %eax, %eax
7FFD3204068C: 74 39                      je     0x7ffd320406c7  ; <+231>
7FFD3204068E: 48 8B 05 4B 51 4F 00       movq   0x4f514b(%rip), %rax
7FFD32040695: 48 8B 00                   movq   (%rax), %rax
7FFD32040698: 48 85 C0                   testq  %rax, %rax
7FFD3204069B: 74 2A                      je     0x7ffd320406c7  ; <+231>
7FFD3204069D: 49 BA 70 BB D5 1A EB 1F >  movabsq $-0x2bc2e014e52a4490, %r10  ; imm = 0xD43D1FEB1AD5BB70 
7FFD320406A7: 48 8D 94 24 98 00 00 00    leaq   0x98(%rsp), %rdx
7FFD320406AF: 48 8D 0D 2A C1 3B 00       leaq   0x3bc12a(%rip), %rcx
7FFD320406B6: FF 15 54 B0 3A 00          callq  *0x3ab054(%rip)
7FFD320406BC: 85 C0                      testl  %eax, %eax
7FFD320406BE: 74 07                      je     0x7ffd320406c7  ; <+231>
7FFD320406C0: 0B BC 24 98 00 00 00       orl    0x98(%rsp), %edi
7FFD320406C7: 48 85 F6                   testq  %rsi, %rsi
7FFD320406CA: 0F 84 D6 00 00 00          je     0x7ffd320407a6  ; <+454>
7FFD320406D0: 48 83 3E 00                cmpq   $0x0, (%rsi)
7FFD320406D4: 74 09                      je     0x7ffd320406df  ; <+255>
7FFD320406D6: 4D 85 F6                   testq  %r14, %r14
7FFD320406D9: 0F 84 C7 00 00 00          je     0x7ffd320407a6  ; <+454>
7FFD320406DF: 48 8D 9C 24 98 00 00 00    leaq   0x98(%rsp), %rbx
7FFD320406E7: 40 F6 C7 01                testb  $0x1, %dil
7FFD320406EB: 74 15                      je     0x7ffd32040702  ; <+290>
7FFD320406ED: C7 84 24 98 00 00 00 20 >  movl   $0x20, 0x98(%rsp)
7FFD320406F8: 48 8D 9C 24 9C 00 00 00    leaq   0x9c(%rsp), %rbx
7FFD32040700: EB 33                      jmp    0x7ffd32040735  ; <+341>
7FFD32040702: 48 FF 15 9F A5 3A 00       callq  *0x3aa59f(%rip)
7FFD32040709: 0F 1F 44 00 00             nopl   (%rax,%rax)
7FFD3204070E: 85 C0                      testl  %eax, %eax
7FFD32040710: 74 23                      je     0x7ffd32040735  ; <+341>
7FFD32040712: 80 3D 87 09 4F 00 00       cmpb   $0x0, 0x4f0987(%rip)
7FFD32040719: 75 1A                      jne    0x7ffd32040735  ; <+341>
7FFD3204071B: 48 8D 0D DE C0 3B 00       leaq   0x3bc0de(%rip), %rcx
7FFD32040722: 48 FF 15 67 A5 3A 00       callq  *0x3aa567(%rip)
7FFD32040729: 0F 1F 44 00 00             nopl   (%rax,%rax)
7FFD3204072E: C6 05 6B 09 4F 00 01       movb   $0x1, 0x4f096b(%rip)
7FFD32040735: 48 8D 84 24 98 00 00 00    leaq   0x98(%rsp), %rax
7FFD3204073D: 48 2B D8                   subq   %rax, %rbx
7FFD32040740: 48 C1 FB 02                sarq   $0x2, %rbx
7FFD32040744: 48 39 1E                   cmpq   %rbx, (%rsi)
7FFD32040747: 72 3D                      jb     0x7ffd32040786  ; <+422>
7FFD32040749: 48 89 1E                   movq   %rbx, (%rsi)
7FFD3204074C: 48 85 DB                   testq  %rbx, %rbx
7FFD3204074F: 74 18                      je     0x7ffd32040769  ; <+393>
7FFD32040751: 4C 8D 04 9D 00 00 00 00    leaq   (,%rbx,4), %r8
7FFD32040759: 48 8D 94 24 98 00 00 00    leaq   0x98(%rsp), %rdx
7FFD32040761: 49 8B CE                   movq   %r14, %rcx
7FFD32040764: E8 63 5D 36 00             callq  0x7ffd323a64cc  ; <+3563244>
7FFD32040769: 33 C0                      xorl   %eax, %eax
7FFD3204076B: EB 07                      jmp    0x7ffd32040774  ; <+404>
7FFD3204076D: 8B 84 24 90 00 00 00       movl   0x90(%rsp), %eax
7FFD32040774: 48 8B 9C 24 A0 00 00 00    movq   0xa0(%rsp), %rbx
7FFD3204077C: 48 83 C4 70                addq   $0x70, %rsp
7FFD32040780: 41 5E                      popq   %r14
7FFD32040782: 5F                         popq   %rdi
7FFD32040783: 5E                         popq   %rsi
7FFD32040784: C3                         retq   
7FFD32040785: CC                         int3   
7FFD32040786: BA 7A 00 07 80             movl   $0x8007007a, %edx  ; imm = 0x8007007A 
7FFD3204078B: 48 8D 4C 24 30             leaq   0x30(%rsp), %rcx
7FFD32040790: E8 9F 39 00 00             callq  0x7ffd32044134  ; <+15188>
7FFD32040795: 48 8D 15 4C F6 4D 00       leaq   0x4df64c(%rip), %rdx  ; D3D12SDKVersion + 1191704
7FFD3204079C: 48 8D 4C 24 30             leaq   0x30(%rsp), %rcx
7FFD320407A1: E8 AA 99 28 00             callq  0x7ffd322ca150  ; <+2661232>
7FFD320407A6: BA FF FF 00 80             movl   $0x8000ffff, %edx  ; imm = 0x8000FFFF 
7FFD320407AB: 48 8D 4C 24 50             leaq   0x50(%rsp), %rcx
7FFD320407B0: E8 7F 39 00 00             callq  0x7ffd32044134  ; <+15188>
7FFD320407B5: 48 8D 15 2C F6 4D 00       leaq   0x4df62c(%rip), %rdx  ; D3D12SDKVersion + 1191704
7FFD320407BC: 48 8D 4C 24 50             leaq   0x50(%rsp), %rcx
7FFD320407C1: E8 8A 99 28 00             callq  0x7ffd322ca150  ; <+2661232>
7FFD320407C6: CC                         int3   
7FFD320407C7: CC                         int3   
7FFD320407C8: CC                         int3   
7FFD320407C9: CC                         int3   
7FFD320407CA: CC                         int3   
7FFD320407CB: CC                         int3   
7FFD320407CC: CC                         int3   
7FFD320407CD: CC                         int3   
7FFD320407CE: CC                         int3   
7FFD320407CF: CC                         int3   
7FFD320407D0: 40 57                      pushq  %rdi
7FFD320407D2: 48 83 EC 40                subq   $0x40, %rsp
7FFD320407D6: 48 C7 44 24 20 FE FF FF >  movq   $-0x2, 0x20(%rsp)
7FFD320407DF: 48 89 5C 24 50             movq   %rbx, 0x50(%rsp)
7FFD320407E4: 8B C2                      movl   %edx, %eax
7FFD320407E6: 33 FF                      xorl   %edi, %edi
7FFD320407E8: 85 D2                      testl  %edx, %edx
7FFD320407EA: 0F 84 29 01 00 00          je     0x7ffd32040919  ; <+825>
7FFD320407F0: 83 F8 01                   cmpl   $0x1, %eax
7FFD320407F3: 74 0E                      je     0x7ffd32040803  ; <+547>
7FFD320407F5: 83 FA 01                   cmpl   $0x1, %edx
7FFD320407F8: 0F 85 3B 02 00 00          jne    0x7ffd32040a39  ; <+1113>
7FFD320407FE: E9 04 01 00 00             jmp    0x7ffd32040907  ; <+807>
7FFD32040803: 48 89 7C 24 68             movq   %rdi, 0x68(%rsp)
7FFD32040808: 49 BA 70 BB 5A 34 C6 06 >  movabsq $-0x516ef939cba54490, %r10  ; imm = 0xAE9106C6345ABB70 
7FFD32040812: 48 8D 54 24 68             leaq   0x68(%rsp), %rdx
7FFD32040817: 48 8D 0D 72 C6 3B 00       leaq   0x3bc672(%rip), %rcx
7FFD3204081E: 48 8B 05 9B B3 4E 00       movq   0x4eb39b(%rip), %rax
7FFD32040825: FF 15 E5 AE 3A 00          callq  *0x3aaee5(%rip)
7FFD3204082B: 85 C0                      testl  %eax, %eax
7FFD3204082D: 78 7A                      js     0x7ffd320408a9  ; <+713>
7FFD3204082F: B9 18 00 00 00             movl   $0x18, %ecx
7FFD32040834: E8 C3 8B 28 00             callq  0x7ffd322c93fc  ; <+2657820>
7FFD32040839: 48 8B D8                   movq   %rax, %rbx
7FFD3204083C: 48 89 44 24 30             movq   %rax, 0x30(%rsp)
7FFD32040841: 48 8D 05 30 51 39 00       leaq   0x395130(%rip), %rax
7FFD32040848: 48 89 03                   movq   %rax, (%rbx)
7FFD3204084B: C7 43 08 01 00 00 00       movl   $0x1, 0x8(%rbx)
7FFD32040852: E8 39 0E 0E 00             callq  0x7ffd32121690  ; <+921776>
7FFD32040857: 48 89 43 10                movq   %rax, 0x10(%rbx)
7FFD3204085B: 48 8B 4C 24 68             movq   0x68(%rsp), %rcx
7FFD32040860: 48 8B 01                   movq   (%rcx), %rax
7FFD32040863: 0F 10 05 4E BE 3B 00       movups 0x3bbe4e(%rip), %xmm0
7FFD3204086A: F3 0F 7F 44 24 30          movdqu %xmm0, 0x30(%rsp)
7FFD32040870: 49 BA 70 B1 5D 58 8F 07 >  movabsq $-0x52dff870a7a24e90, %r10  ; imm = 0xAD20078F585DB170 
7FFD3204087A: 4C 8B C3                   movq   %rbx, %r8
7FFD3204087D: 48 8D 54 24 30             leaq   0x30(%rsp), %rdx
7FFD32040882: 48 8B 80 40 01 00 00       movq   0x140(%rax), %rax
7FFD32040889: FF 15 81 AE 3A 00          callq  *0x3aae81(%rip)
7FFD3204088F: 48 8B 03                   movq   (%rbx), %rax
7FFD32040892: 49 BA 70 B1 5E 36 10 1F >  movabsq $-0x4553e0efc9a14e90, %r10  ; imm = 0xBAAC1F10365EB170 
7FFD3204089C: 48 8B CB                   movq   %rbx, %rcx
7FFD3204089F: 48 8B 40 10                movq   0x10(%rax), %rax
7FFD320408A3: FF 15 67 AE 3A 00          callq  *0x3aae67(%rip)
7FFD320408A9: C6 05 01 08 4F 00 01       movb   $0x1, 0x4f0801(%rip)
7FFD320408B0: 8B 05 5A 8C 4F 00          movl   0x4f8c5a(%rip), %eax
7FFD320408B6: 85 C0                      testl  %eax, %eax
7FFD320408B8: 75 11                      jne    0x7ffd320408cb  ; <+747>
7FFD320408BA: E8 D5 7B 20 00             callq  0x7ffd32248494  ; <+2129588>
7FFD320408BF: 89 05 4F 8C 4F 00          movl   %eax, 0x4f8c4f(%rip)
7FFD320408C5: 8B 05 45 8C 4F 00          movl   0x4f8c45(%rip), %eax
7FFD320408CB: FF C0                      incl   %eax
7FFD320408CD: 89 05 3D 8C 4F 00          movl   %eax, 0x4f8c3d(%rip)
7FFD320408D3: 48 8D 0D F6 BA 4E 00       leaq   0x4ebaf6(%rip), %rcx
7FFD320408DA: E8 A1 36 00 00             callq  0x7ffd32043f80  ; <+14752>
7FFD320408DF: E8 E0 35 00 00             callq  0x7ffd32043ec4  ; <+14564>
7FFD320408E4: 90                         nop    
7FFD320408E5: 48 8B 4C 24 68             movq   0x68(%rsp), %rcx
7FFD320408EA: 48 85 C9                   testq  %rcx, %rcx
7FFD320408ED: 74 18                      je     0x7ffd32040907  ; <+807>
7FFD320408EF: 48 8B 01                   movq   (%rcx), %rax
7FFD320408F2: 49 BA 70 B1 5E 36 10 1F >  movabsq $-0x4553e0efc9a14e90, %r10  ; imm = 0xBAAC1F10365EB170 
7FFD320408FC: 48 8B 40 10                movq   0x10(%rax), %rax
7FFD32040900: FF 15 0A AE 3A 00          callq  *0x3aae0a(%rip)
7FFD32040906: 90                         nop    
7FFD32040907: 40 38 3D A2 07 4F 00       cmpb   %dil, 0x4f07a2(%rip)
7FFD3204090E: 0F 84 25 01 00 00          je     0x7ffd32040a39  ; <+1113>
7FFD32040914: E9 25 01 00 00             jmp    0x7ffd32040a3e  ; <+1118>
7FFD32040919: 48 39 3D 88 07 4F 00       cmpq   %rdi, 0x4f0788(%rip)
7FFD32040920: 74 10                      je     0x7ffd32040932  ; <+850>
7FFD32040922: 4D 85 C0                   testq  %r8, %r8
7FFD32040925: 0F 95 C1                   setne  %cl
7FFD32040928: E8 0B FC FF FF             callq  0x7ffd32040538  ; D3D12RegisterLayers + 216
7FFD3204092D: 90                         nop    
7FFD3204092E: EB 02                      jmp    0x7ffd32040932  ; <+850>
7FFD32040930: 33 FF                      xorl   %edi, %edi
7FFD32040932: 48 89 7C 24 68             movq   %rdi, 0x68(%rsp)
7FFD32040937: 49 BA 70 BB 5A 34 C6 06 >  movabsq $-0x516ef939cba54490, %r10  ; imm = 0xAE9106C6345ABB70 
7FFD32040941: 48 8D 54 24 68             leaq   0x68(%rsp), %rdx
7FFD32040946: 48 8D 0D 43 C5 3B 00       leaq   0x3bc543(%rip), %rcx
7FFD3204094D: 48 8B 05 6C B2 4E 00       movq   0x4eb26c(%rip), %rax
7FFD32040954: FF 15 B6 AD 3A 00          callq  *0x3aadb6(%rip)
7FFD3204095A: 85 C0                      testl  %eax, %eax
7FFD3204095C: 78 31                      js     0x7ffd3204098f  ; <+943>
7FFD3204095E: 48 8B 4C 24 68             movq   0x68(%rsp), %rcx
7FFD32040963: 48 8B 01                   movq   (%rcx), %rax
7FFD32040966: 0F 10 05 4B BD 3B 00       movups 0x3bbd4b(%rip), %xmm0
7FFD3204096D: F3 0F 7F 44 24 30          movdqu %xmm0, 0x30(%rsp)
7FFD32040973: 49 BA 70 13 D5 10 06 AF >  movabsq $-0x7b4750f9ef2aec90, %r10  ; imm = 0x84B8AF0610D51370 
7FFD3204097D: 48 8D 54 24 30             leaq   0x30(%rsp), %rdx
7FFD32040982: 48 8B 80 48 01 00 00       movq   0x148(%rax), %rax
7FFD32040989: FF 15 81 AD 3A 00          callq  *0x3aad81(%rip)
7FFD3204098F: 40 38 3D 1B 07 4F 00       cmpb   %dil, 0x4f071b(%rip)
7FFD32040996: 74 61                      je     0x7ffd320409f9  ; <+1049>
7FFD32040998: 83 05 71 8B 4F 00 FF       addl   $-0x1, 0x4f8b71(%rip)
7FFD3204099F: 75 58                      jne    0x7ffd320409f9  ; <+1049>
7FFD320409A1: 39 3D 6D 8B 4F 00          cmpl   %edi, 0x4f8b6d(%rip)
7FFD320409A7: 7C 50                      jl     0x7ffd320409f9  ; <+1049>
7FFD320409A9: 48 8B 0D F0 63 4F 00       movq   0x4f63f0(%rip), %rcx
7FFD320409B0: 48 85 C9                   testq  %rcx, %rcx
7FFD320409B3: 74 44                      je     0x7ffd320409f9  ; <+1049>
7FFD320409B5: 48 8B 01                   movq   (%rcx), %rax
7FFD320409B8: 49 BA 70 3B 5B 5E 1B 0F >  movabsq $-0x7ddbf0e4a1a4c490, %r10  ; imm = 0x82240F1B5E5B3B70 
7FFD320409C2: 33 D2                      xorl   %edx, %edx
7FFD320409C4: 48 8B 00                   movq   (%rax), %rax
7FFD320409C7: FF 15 43 AD 3A 00          callq  *0x3aad43(%rip)
7FFD320409CD: 48 8B 0D D4 63 4F 00       movq   0x4f63d4(%rip), %rcx
7FFD320409D4: 48 8B 01                   movq   (%rcx), %rax
7FFD320409D7: 49 BA 70 98 D2 76 A5 1E >  movabsq $-0x34c2e15a892d6790, %r10  ; imm = 0xCB3D1EA576D29870 
7FFD320409E1: 48 8B 15 B8 63 4F 00       movq   0x4f63b8(%rip), %rdx
7FFD320409E8: 48 8B 40 28                movq   0x28(%rax), %rax
7FFD320409EC: FF 15 1E AD 3A 00          callq  *0x3aad1e(%rip)
7FFD320409F2: 48 89 3D A7 63 4F 00       movq   %rdi, 0x4f63a7(%rip)
7FFD320409F9: 48 8B 05 E0 B9 4E 00       movq   0x4eb9e0(%rip), %rax
7FFD32040A00: 48 8B 48 20                movq   0x20(%rax), %rcx
7FFD32040A04: 89 38                      movl   %edi, (%rax)
7FFD32040A06: 48 89 78 20                movq   %rdi, 0x20(%rax)
7FFD32040A0A: 48 FF 15 9F AC 3A 00       callq  *0x3aac9f(%rip)
7FFD32040A11: 0F 1F 44 00 00             nopl   (%rax,%rax)
7FFD32040A16: 90                         nop    
7FFD32040A17: 48 8B 4C 24 68             movq   0x68(%rsp), %rcx
7FFD32040A1C: 48 85 C9                   testq  %rcx, %rcx
7FFD32040A1F: 74 18                      je     0x7ffd32040a39  ; <+1113>
7FFD32040A21: 48 8B 01                   movq   (%rcx), %rax
7FFD32040A24: 49 BA 70 B1 5E 36 10 1F >  movabsq $-0x4553e0efc9a14e90, %r10  ; imm = 0xBAAC1F10365EB170 
7FFD32040A2E: 48 8B 40 10                movq   0x10(%rax), %rax
7FFD32040A32: FF 15 D8 AC 3A 00          callq  *0x3aacd8(%rip)
7FFD32040A38: 90                         nop    
7FFD32040A39: BF 01 00 00 00             movl   $0x1, %edi
7FFD32040A3E: 8B C7                      movl   %edi, %eax
7FFD32040A40: 48 8B 5C 24 50             movq   0x50(%rsp), %rbx
7FFD32040A45: 48 83 C4 40                addq   $0x40, %rsp
7FFD32040A49: 5F                         popq   %rdi
7FFD32040A4A: C3                         retq   
7FFD32040A4B: CC                         int3   
7FFD32040A4C: CC                         int3   
7FFD32040A4D: CC                         int3   
7FFD32040A4E: CC                         int3   
7FFD32040A4F: CC                         int3   
7FFD32040A50: CC                         int3   
7FFD32040A51: CC                         int3   
7FFD32040A52: CC                         int3   
7FFD32040A53: CC                         int3   
7FFD32040A54: 48 83 EC 38                subq   $0x38, %rsp
7FFD32040A58: 48 C7 44 24 20 FE FF FF >  movq   $-0x2, 0x20(%rsp)
7FFD32040A61: 48 8B 09                   movq   (%rcx), %rcx
7FFD32040A64: 48 85 C9                   testq  %rcx, %rcx
7FFD32040A67: 74 18                      je     0x7ffd32040a81  ; <+1185>
7FFD32040A69: 48 8B 01                   movq   (%rcx), %rax
7FFD32040A6C: 49 BA 70 B1 5E 36 10 1F >  movabsq $-0x4553e0efc9a14e90, %r10  ; imm = 0xBAAC1F10365EB170 
7FFD32040A76: 48 8B 40 10                movq   0x10(%rax), %rax
7FFD32040A7A: FF 15 90 AC 3A 00          callq  *0x3aac90(%rip)
7FFD32040A80: 90                         nop    
7FFD32040A81: 48 83 C4 38                addq   $0x38, %rsp
7FFD32040A85: C3                         retq   
7FFD32040A86: CC                         int3   
7FFD32040A87: CC                         int3   
7FFD32040A88: 71 99                      jno    0x7ffd32040a23  ; <+1091>

Platform: Microsoft Windows 11 Home Version 10.0.22631 Build 22631 Intel i9 12900H 32 GB RAM @ 3200 MHz NVidia GeForce RTX 3070 Ti Laptop GPU

myth0genesis commented 3 days ago

I found out the issue is associated with using a present_mode in wgpu::SurfaceConfiguration of wgpu::PresentMode::Fifo in my specific case. I still can't figure out why it was working for several days and then suddenly stopped, though. The fix was to set present_mode to wgpu::PresentMode::AutoNoVsync. I'm a bit reluctant to close this issue since Fifo just seemed to randomly stop working with configure(), so I'll probably leave this open for a few more days to see if anyone has a better idea of what's happening here.

myth0genesis commented 2 days ago

Update: So wgpu::PresentMode::Fifo does work if I switch the backends field in the wgpu::InstanceDescriptor to wgpu::Backends::VULKAN. I've also tried GL with no issues. So this seems to only break for the DX12 backend. I don't have a platform to test Metal on, so I can't speak for that, but I'm going to leave this open for longer in hopes that some more eyes get on it and maybe some folks can test on Metal, too.