I never used VPI yet, but from what I understand the idea is that if you do NOT want to write any VHDL testbench code but do want to verify your VHDL DUT purely with software, that is where VPI will need to be utilized for GHDL.
But browsing the quickstart example, I do see that the script file compiles ent.vhd but also tb.vhd
so I am confused now, what is tb.vhd doing there? why we have basic testbench there? shouldn't the example supposed to be of such a type where I toggle/read top level port pins of ent.vhd using purely C?
or what am I missing here?
Another question here would be, if I am planning to use VPI to drive and read pins of my VHDL DUT using C, how would I go about plotting all/any signals with GTKWave within deep levels of DUT as well as plotting top DUT's port pins? Would that be doable?
And one more question is - I saw somewhere here mentioning that accessing arrays/records through VPI is not supported in GHDL, so does it mean I cannot access/view std_logic_vectors declared as top ports in my DUT? what about plotting some std_logic_vector deep inside DUT hierarchy?
I never used VPI yet, but from what I understand the idea is that if you do NOT want to write any VHDL testbench code but do want to verify your VHDL DUT purely with software, that is where VPI will need to be utilized for GHDL.
But browsing the quickstart example, I do see that the script file compiles ent.vhd but also tb.vhd so I am confused now, what is tb.vhd doing there? why we have basic testbench there? shouldn't the example supposed to be of such a type where I toggle/read top level port pins of ent.vhd using purely C?
or what am I missing here?
Another question here would be, if I am planning to use VPI to drive and read pins of my VHDL DUT using C, how would I go about plotting all/any signals with GTKWave within deep levels of DUT as well as plotting top DUT's port pins? Would that be doable?
And one more question is - I saw somewhere here mentioning that accessing arrays/records through VPI is not supported in GHDL, so does it mean I cannot access/view std_logic_vectors declared as top ports in my DUT? what about plotting some std_logic_vector deep inside DUT hierarchy?