library ieee;
use ieee.std_logic_1164.all;
use ieee.std_logic_arith.all;
entity counters_8 is
generic (MAX : integer := 12);
port(C, CLR : in std_logic;
Q : out integer range 0 to MAX-1);
end counters_8;
architecture archi of counters_8 is
signal cnt : integer range 0 to MAX-1;
begin
process (C, CLR)
begin
if (CLR='1') then
cnt <= 0;
elsif (rising_edge(C)) then
cnt <= (cnt + 1) mod MAX ;
end if;
end process;
Q <= cnt;
end archi;
I was verifying GHDL
--synth
and theghdl-yosys-plugin
with examples from Xilinx. I found a problem with a file for ISE, called counters_8.vhd, which fails only with the plugin: