Open rlee287 opened 4 years ago
Of course, that's something that would be great. As it doesn't require any knowledge of ghdl, I think this could be a contribution from anyone interested. Just start from the existing write_verilog command of yosys.
I am going through the write_verilog
file now to see how it is structured and what kinds of changes would be necessary. However, it also looks like ghdl --synth
outputs VHDL to the standard output. Would it make more sense to try to repurpose some of the code from ghdl --synth
, or would it be better to work directly with RTLIL the way write_verilog
does?
The code from ghdl that writes the vhdl netlist is written in Ada, so you cannot repurpose it without rewriting it. But you could get inspiration from it!
The most difficult issue is how to deal with identifiers. The names in the netlist can be invalid vhdl names (like all the ones that start with $), can be vhdl keywords or can be correct identifiers. An easy way to deal with this issue is to always use extended identifiers. That would be a first good step.
The second issue is to deal with sign extension. The yosys operators can implicitly extended their operands, and that should become explicit in vhdl.
The third issue is to deal with some particularities. In vhdl, there are functions to add signed or unsigned vectors, but not for bits.
The code that turns VHDL into a netlist is also written in Ada, so shouldn't it be possible to create a bridge in the other direction as well?
Yes, but that would be a different project: adding an importer from yosys netlist to the ghdl netlist.
Possible, my in my opinion less useful or more difficult to use.
This would greatly help with simulating mixed-language projects, which could look like the following:
Verilog testbench (which should be possible now):
write_verilog
the top module.VHDL testbench (which would be made possible by the command suggested above):
ghdl_write_vhdl
the top module.