ghdl / ghdl-yosys-plugin

VHDL synthesis (based on ghdl)
GNU General Public License v3.0
304 stars 31 forks source link

Fix $pmux port order #118

Closed Xiretza closed 4 years ago

Xiretza commented 4 years ago

Therefore, the inputs need to be appended to the data vector in ascending order, such that IN(2) is assigned to B[WIDTH-1:0], IN(3) to B[2*WIDTH-1:WIDTH], etc.

tgingold commented 4 years ago

Thanks!