Closed alemuller closed 4 years ago
library ieee; use ieee.std_logic_1164.all; entity issue is port (foo, bar : in std_logic_vector(7 downto 0)); end issue; architecture beh of issue is begin assert foo = bar; end architecture beh;
Yosys 0.9+2406 (git sha1 27b7ffc7, gcc 10.1.0 -fPIC -Os) -- Running command `ghdl --std=08 -fpsl issue_extract.vhdl -e issue' --
GHDL 1.0-dev (v0.37.0-560-ge5db9760) [Dunoon edition]
Wrong ghdl-yosis-plugin version. It works now.