I've downloaded old FP adder to test the synthesis, it uses synopsys packages.
So I've run synthesis in yosys + module.so mode.
Command:
ghdl --ieee=synopsys -fexplicit fpadd_normalize_struct.vhd -e FPadd_normalize
The output is:
Executing GHDL.
ERROR: vhdl import failed.
without explicit flag it seems to see all the syntax, the output is:
Executing GHDL.
fpadd_normalize_struct.vhd:145:56:error: operator ""="" is overloaded
fpadd_normalize_struct.vhd:145:56:error: possible interpretations are:
../../src/synopsys/std_logic_unsigned.vhdl:64:14:error: function "=" [std_logic_vector, std_logic_vector return boolean]
../../src/ieee/v93/std_logic_1164.vhdl:90:8:error: function "=" [std_logic_vector, std_logic_vector return boolean]
fpadd_normalize_struct.vhd:145:56:error: (you may want to use the -fexplicit option)
fpadd_normalize_struct.vhd:148:59:error: operator ""/="" is overloaded
fpadd_normalize_struct.vhd:148:59:error: possible interpretations are:
../../src/synopsys/std_logic_unsigned.vhdl:68:14:error: function "/=" [std_logic_vector, std_logic_vector return boolean]
../../src/ieee/v93/std_logic_1164.vhdl:90:8:error: function "/=" [std_logic_vector, std_logic_vector return boolean]
ERROR: vhdl import failed.
I definitely remember that i synthesized long ago in some commercial product.
I've downloaded old FP adder to test the synthesis, it uses synopsys packages. So I've run synthesis in yosys + module.so mode. Command:
ghdl --ieee=synopsys -fexplicit fpadd_normalize_struct.vhd -e FPadd_normalize
The output is:
without explicit flag it seems to see all the syntax, the output is:
I definitely remember that i synthesized long ago in some commercial product.
fpadd_normalize_struct.vhd.zip