Open Chopper455 opened 4 years ago
eine
commented
4 years ago In-compiled it directly into the yosys 334ec5fa.
Does this mean that you tried https://github.com/ghdl/ghdl-yosys-plugin#build-as-part-of-yosys-not-recommended instead of https://github.com/ghdl/ghdl-yosys-plugin#build-as-a-module-shared-library?
tgingold
commented
4 years ago I will first fix the missing features, but:
Chopper455
commented
4 years ago yes, i've tried #build-as-part-of-yosys-not-recommended because i couldn't compile it as module because of missing yosys symbols during linking, it was easier for me just to integrate it in yosys to make symbols visible. In the future i'll create separate issues, thank you.
Chopper455
commented
4 years ago i'm not in a VHDL camp so i'm not familiar with lexical/syntax rules in standard, i consulted Quartus to verify them for me.
Used msys2 32bit in Windows 7 to integrate everything together. I've compiled ghdl 81905a8c. Then used ghdl-yosys-plugin 0b687cd. In-compiled it directly into the yosys 334ec5fa. fails.zip I hope this will help you to make this piece of work even better:)
Used several designs from opencores.org, to check if they really can be synthesized used Quartus Prime Lite Edition 16.1. Some designs where ghdl falls with "GHDL Bug occurred" weren't checked in Quartus.
https://opencores.org/projects/8b10b_encdec Command:
ghdl ./8b10_enc.vhd -eResult:https://opencores.org/projects/802154phycore In Quartus used "ieee_802_15_4_phy" top-module, but in ghdl used a lower level module. Command:
ghdl -fsynopsys -fexplicit ./chip_gen.vhd ./upsampler.vhd ./tx_fir.vhd ./tx_core.vhd -eResult:https://opencores.org/projects/avs_aes Quartus compiled fine the AES_CORE top-module. Command:
ghdl --work=avs_aes_lib ./addroundkey.vhd ./aes_core.vhd ./aes_fsm_decrypt.vhd ./aes_fsm_encrypt.vhd ./avs_aes.vhd ./avs_aes_pkg.vhd ./keyexpansionV2.vhd ./memory_word.vhd ./mixcol.vhd ./mixcol_fwd.vhd ./mixcol_inv.vhd ./mux3.vhd ./sbox.vhd ./sbox_arch1.vhd ./shiftrow.vhd ./shiftrow_fwd.vhd ./shiftrow_inv.vhd -eResult:https://opencores.org/projects/cordic Command:
ghdl -fsynopsys ./r2p_pre.vhd -eResult:Command:
ghdl -fsynopsys ./r2p_post.vhd -eResult:https://opencores.org/projects/fft_fir_filter Command:
ghdl -fsynopsys ./alfft_core_slip.vhd -eResult:https://opencores.org/projects/fpu_double Command:
ghdl -fsynopsys -fexplicit ./fpupack.vhd ./fpu_sub.vhd -eResult:https://opencores.org/projects/hilbert_transformer Command:
ghdl -fsynopsys ./fsf_comb_filter.vhd -eResult:https://opencores.org/projects/i2c_master_slave Command:
ghdl -fsynopsys ./i2c_core_v02.vhd -eResult:https://opencores.org/projects/iicmb Command:
ghdl ./iicmb_int_pkg.vhd ./mbit.vhd -eResult:https://opencores.org/projects/neo430 Command:
ghdl --work=neo430 ./neo430_package.vhd ./neo430_timer.vhd -eResult:https://opencores.org/projects/plasma Command:
ghdl -fsynopsys -fexplicit ./mlite_pack.vhd ./ram.vhd -eResult:https://opencores.org/projects/cpu6502_true_cycle Command:
ghdl -fsynopsys ./fsm_execution_unit.vhd -eResult:https://opencores.org/projects/usb11_phy_translation Command:
ghdl -fsynopsys -fexplicit ./usb_tx_phy.vhdl -eResult:https://opencores.org/projects/viterbi_decoder_axi4s Quartus sythesized with "dec_viterbi" as a top-module, maybe I just set library name incorrectly. Command:
ghdl -fsynopsys --work=dec_viterbi ./acs.vhd ./axi4s_buffer.vhd ./branch_distance.vhd ./dec_viterbi.vhd ./generic_sp_ram.vhd ./pkg_components.vhd ./pkg_helper.vhd ./pkg_param.vhd ./pkg_param_derived.vhd ./pkg_trellis.vhd ./pkg_types.vhd ./ram_ctrl.vhd ./recursion.vhd ./reorder.vhd ./traceback.vhd -eResult:renamed the entity, tried again Command:
ghdl -fsynopsys --work=dec_viterbi ./acs.vhd ./axi4s_buffer.vhd ./branch_distance.vhd ./dec_viterbi_rename.vhd ./generic_sp_ram.vhd ./pkg_components.vhd ./pkg_helper.vhd ./pkg_param.vhd ./pkg_param_derived.vhd ./pkg_trellis.vhd ./pkg_types.vhd ./ram_ctrl.vhd ./recursion.vhd ./reorder.vhd ./traceback.vhd -eResult: