Closed sambazley closed 3 years ago
This error is produced when compiling:
process (DIN_CLK, CLK_OUT) begin if rising_edge(DIN_CLK) then OPUT_RDY <= '1'; end if; if rising_edge(CLK_OUT) then OPUT_RDY <= '0'; end if; end process;
The error message could be better but you are trying to synthesize a multi-clock FF, which is not supported by yosys.
I'll find another way to do it then. Thanks for your help.
This error is produced when compiling: