Exiting with 'wire not found for $posedge'

Dear ghdl-yosys-plugin project, first of all thank you for your great work so far. I have a minimal example I can reproduce the 'ERROR: wire not found for $posedge' :

use IEEE.std_logic_1164.all;
use IEEE.numeric_std.all;

entity test is  
    port (
        resb:                           in std_logic;                 
        clk_FF:                         in std_logic;
        ADD_FF:                         in unsigned(1 downto 0); 
        CONFIG:                         in std_logic;
        D_FF:                           in std_logic;
        WE:                             in std_logic;
        EN_signal:                      out std_logic
        );
end test;

architecture test_a of test is  
signal Q_FF: std_logic_vector(0 to 1);         
begin   
    process(resb, clk_FF)
    begin
    if resb = '0' then  
        Q_FF <= "00";
    elsif clk_FF'event and clk_FF = '1' then
        if WE = '1' then
            Q_FF(to_integer(ADD_FF)) <= D_FF;   
        end if;
    end if;
     end process;       

    process(CONFIG, Q_FF)
    begin 
        if CONFIG = '1'  then
            EN_signal <=  Q_FF(0);
         else
            EN_signal <= '0';
         end if;                                
      end process;  
end;

Running this with yosys -m ghdl -p 'ghdl ./test/test.vhd -e test'

-- Running command `ghdl ./test/test.vhd -e test' --

Executing GHDL. Importing module test. ERROR: wire not found for $posedge

I also tested with ghdl --synth test/test.vhd -e test This produces output without any error message. I know that the style of this may not be perfect but constructs like this appear in a very large project that cannot be easily rewritten.

ghdl / ghdl-yosys-plugin

Exiting with 'wire not found for $posedge' #128