Open IIupor opened 3 years ago
VHDL being case insensitive, ghdl only uses lowercase names. Yosys being verilog is case sensitive and expect the same name.
So, you can either use lowercase ports name in verilog (that should work), or rename the ports once imported (using the command rename in yosys).
I fear there is no magic solution.
Thank you for the answer
Description ghdl or yosys changes module port names to lowercase
Expected behaviour I want to use the module (i.e. entity) mux2_1 in mux4_1 and mux4_1_x2. Using
i got error
ERROR: Re-definition of module `\ mux2_1 '
Using
ghdl mux2_1.vhd mux4_1.vhd -e mux4_1
i got errorERROR: Module `mux2_1 'referenced in module` mux4_1_x2' in cell `mux1 'does not have a port named' Y '.
To determine the cause of the error, I wrote verilog file with the following command:
write_verilog ./mux4_1_x2.syn0.v
It turned out that ghdl or yosys changed the port names of the module to lower case
How can a module be used in different files?
How to reproduce?