Mixed synthesis with a Verilog top-level fails when parameters are specified

[rodrigomelo9]

Hi. We (@eine) were testing mixed synthesis cases.

• Verilog + VHDL (top) works (note: the Verilog module must be specified as component into the VHDL).
• VHDL + Verilog (top) works when generics are not specified in the instantiation
• VHDL + Verilog (top) fails when generics are specified in the instantiation:

ERROR: Module `Blinking' referenced in module `Top' in cell `dut' does not have a parameter named 'SECS'.

I tried also with lowercases (changed to secs), without success.

Files to reproduce the issue here (you can execute run.sh, which uses ghdl/synth:beta).

[AndrewD]

I'm integrating a VHDL module into litex that uses generics - any pointers to if this is a relatively isolated issue I can look in to in the GHDL plugin? Otherwise I'll hack it together with Python in the litex integration...

[tgingold]

No, there is currently no support for setting parameters from verilog. You can wrap the vhdl instances into entities without generics.