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ghdl / ghdl-yosys-plugin

VHDL synthesis (based on ghdl)
GNU General Public License v3.0
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Fix mult18x18d component to match yosys verilog #139

Closed JulianKemmerer closed 3 years ago

JulianKemmerer commented 3 years ago

Fixes the single MULT18X18D component per https://github.com/ghdl/ghdl-yosys-plugin/issues/138

The SRIA+B ports are not used per the issue here YosysHQ/nextpnr#208

I suspect this file needs to be modified a fair amount further to match all the components yosys has at https://github.com/YosysHQ/yosys/blob/5aa35b8992fab8b55c1c1fae793b4ad845fd4c4c/techlibs/ecp5/cells_bb.v

Thanks for the great project!

tgingold commented 3 years ago

Thanks!