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ghdl / ghdl-yosys-plugin

VHDL synthesis (based on ghdl)
GNU General Public License v3.0
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Use of BRAM in ICE40 ... #165

Open PPlinux opened 2 years ago

PPlinux commented 2 years ago

Dear,

can anyone help me using BRAM 512 word, 16 bit as a ROM (RAM preloaded during FPGA power on) using GHDL VHDL -> Yosys -> Lattice ICE40 FPGA please ?

Greetings,

Patrick

kevingoh commented 1 year ago

I am new to the toolchain and am having trouble understanding how the techmap works in the plugin.

I have two entities, one is designed to be ROM while another as RAM. The ROM was mapped to BRAM while the RAM to DFFs.

I have no idea how to change this. Can anyone give some hints?

Thanks in advance.

tgingold commented 1 year ago

There is no ROM in an fpga, so it is expected that a ROM is mapped to a BRAM. If you RAM is not correctly described as a RAM, the synthesizer will use DFFs to implement it.