Error when using inout record

[albydnc]

I declare an entity which has an inout record port. When I run simulation in GHDL, it works as intended. When I try to run it through yosys I get this error:

$ yosys -m ghdl -ql ../model/design.log ../model/design.ys
shift_left.vhd:17:5:warning: no assignment for offsets 1:353 of port "snk"
    snk : inout t_comm_channel;
    ^
shift_left.vhd:18:5:warning: no assignment for offset 0 of port "src"
    src : inout t_comm_channel
    ^
ERROR: wire not found for $inout

The record is defined as:

  type t_comm_channel is record
    ready  : std_logic;
    valid  : std_logic;
    sop    : std_logic;
    eop    : std_logic;
    evid   : unsigned(EVID_BITS - 1 downto 0); 
    evtype : unsigned(7 downto 0);
    size   : unsigned(15 downto 0);
    empty  : unsigned(5 downto 0);
    data   : std_logic_vector(255 downto 0);
  end record;

[tmeissner]

Inout ports of record types don't work with VHDL (pre VHDL-2019) synthesis. You have to split your record in two, one for each direction. This isn't a GHDL limitation, it's more a limitation of the language, which was solved with VHDL-2019 interfaces.

Hmmm, right - it's more a limitation of FPGA-hardware, VHDL itself supports bidirectional records, I use it in simulation for my verification components a lot.

[tgingold]

I can investigate, but I need a reproducer.

[albydnc]

Here you go @tgingold.

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;

package utils is
    type t_comm_channel is record
        valid : std_logic;
        ready : std_logic;
        data  : std_logic_vector(15 downto 0);
    end record;
end package;

library ieee;
use ieee.std_logic_1164.all;
use ieee.numeric_std.all;
use work.utils.all;

entity test is
    port (
        input : inout t_comm_channel;
        output : inout t_comm_channel
    );
end entity;

architecture rtl of test is
begin
    output <= input;
end architecture;

in yosys (with ghdl module loaded), run ghdl --std=08 test.vhdl -e test.