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ghdl / ghdl-yosys-plugin

VHDL synthesis (based on ghdl)
GNU General Public License v3.0
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Add iadff #67

Closed pepijndevos closed 4 years ago

pepijndevos commented 4 years ago

I came across this in https://www.digikey.com/eewiki/pages/viewpage.action?pageId=59507062

Solution blatantly stolen from idff right above it.

However, this does not actually solve the problem because GHDL generates a non-constant init value, which is not supported by Yosys, or any FPGA architecture that I'm aware of.

So actually we will need to find a workaround to synthesis iadff with non-const init to some equivalent circuit with muxes and what not, or GHDL needs to be taught not to make flip-flops with non-constant init values, because they are not synthesizable.

tgingold commented 4 years ago

Thanks. The reset pattern should be quite simple. Feel free to open an issue for that.