Aliased input gets wrong port name in yosys

[Fatsie]

I have the following minimal input file:

library ieee;
use ieee.std_logic_1164.ALL;

entity child is
  port (
    CLK: in std_logic;
    I: in std_logic;
    O: out std_logic
  );
end entity child;

architecture rtl of child is
  signal Ialias: std_logic;
begin
  process (CLK)
  begin
    if rising_edge(CLK) then
      O <= Ialias;
    end if;
  end process;
  Ialias <= I;
end architecture rtl;

library ieee;
use ieee.std_logic_1164.ALL;

entity top is
  port (
    CLK: in std_logic;
    I: in std_logic;
    O: out std_logic
  );
end entity top;

architecture rtl of top is
  component child is
    port (
      CLK: in std_logic;
      I: in std_logic;
      O: out std_logic
    );
  end component child;
begin
  inst : child port map(CLK, I, O);
end architecture rtl;

And run the following script:

#!/bin/sh
opts='--std=08'
testopts="$opts --work=test"
rm -f work*
ghdl -a $opts top.vhdl
ghdl -r $opts top --no-run
echo "top OK"
ghdl --synth $opts top > top_synth.vhdl
ghdl -a $testopts top_synth.vhdl
ghdl -r $testopts top --no-run
echo "synth to VHDL OK"
yosys -m ghdl <<EOF
ghdl $opts top
write_verilog top.v
hierarchy -check -top top
EOF

This gives the following output:

[verhaegs@localhost test_ghdl]$ ./run.sh 
top OK
synth to VHDL OK

 /----------------------------------------------------------------------------\
 |                                                                            |
 |  yosys -- Yosys Open SYnthesis Suite                                       |
 |                                                                            |
 |  Copyright (C) 2012 - 2019  Clifford Wolf <clifford@clifford.at>           |
 |                                                                            |
 |  Permission to use, copy, modify, and/or distribute this software for any  |
 |  purpose with or without fee is hereby granted, provided that the above    |
 |  copyright notice and this permission notice appear in all copies.         |
 |                                                                            |
 |  THE SOFTWARE IS PROVIDED "AS IS" AND THE AUTHOR DISCLAIMS ALL WARRANTIES  |
 |  WITH REGARD TO THIS SOFTWARE INCLUDING ALL IMPLIED WARRANTIES OF          |
 |  MERCHANTABILITY AND FITNESS. IN NO EVENT SHALL THE AUTHOR BE LIABLE FOR   |
 |  ANY SPECIAL, DIRECT, INDIRECT, OR CONSEQUENTIAL DAMAGES OR ANY DAMAGES    |
 |  WHATSOEVER RESULTING FROM LOSS OF USE, DATA OR PROFITS, WHETHER IN AN     |
 |  ACTION OF CONTRACT, NEGLIGENCE OR OTHER TORTIOUS ACTION, ARISING OUT OF   |
 |  OR IN CONNECTION WITH THE USE OR PERFORMANCE OF THIS SOFTWARE.            |
 |                                                                            |
 \----------------------------------------------------------------------------/

 Yosys 0.9+932 (git sha1 ff8529a, gcc 4.8.5 -fPIC -Os)

yosys> ghdl --std=08 top
1. Executing GHDL.
ghdl initialized: 0Importing module top.
Importing module child.

yosys> write_verilog top.v

2. Executing Verilog backend.
Dumping module `\child'.
Dumping module `\top'.

yosys> hierarchy -check -top top

3. Executing HIERARCHY pass (managing design hierarchy).

3.1. Analyzing design hierarchy..
Top module:  \top
Used module:     \child
ERROR: Module `child' referenced in module `top' in cell `inst' does not have a port named 'i'.

The procuded VHDL from synth is OK but the verilog from yosys is the following:

module child(clk, ialias, o);
  reg _0_;
  input clk;
  input ialias;
  output o;
  always @(posedge clk)
      _0_ <= ialias;
  assign o = _0_;
endmodule

module top(clk, i, o);
  wire _0_;
  input clk;
  input i;
  output o;
  child inst (
    .clk(clk),
    .i(i),
    .o(_0_)
  );
  assign o = _0_;
  assign _0_ = _0_;
endmodule

The i input port has been renamed to ialias on the child cell.