Slicing vector from array results in SYSTEM.ASSERTIONS.ASSERT_FAILURE raised

I'm trying to synthesize https://github.com/phase4ground/dvb_fpga/blob/master/rtl/axi_stream_master_adapter.vhd but it was failing. This seems to be enough to trigger the exception:

library ieee;
use ieee.std_logic_1164.all;

entity foo is
  port (
    addr : in integer;
    nibble0 : out std_logic_vector(3 downto 0);
    nibble1 : out std_logic_vector(3 downto 0)
  );
end foo;

architecture foo of foo is

  type data_array_t is array (3 downto 0) of std_logic_vector(7 downto 0);
  signal data_buffer : data_array_t;

begin

  nibble0 <= data_buffer(addr)(3 downto 0);
  nibble1 <= data_buffer(addr)(7 downto 4);

end foo;

root@f75417222768:/src# ghdl --synth rtl/foo.vhd  -e foo
rtl/foo.vhd:35:10:warning: signal "data_buffer" is never assigned and has no default value

******************** GHDL Bug occurred ***************************
Please report this bug on https://github.com/ghdl/ghdl/issues
GHDL release: 0.37-dev (v0.36-1576-g76e2f6b3) [Dunoon edition]
Compiled with GNAT Version: 8.3.0
Target: x86_64-linux-gnu
/src/
Command line:
ghdl --synth rtl/foo.vhd -e foo
Exception SYSTEM.ASSERTIONS.ASSERT_FAILURE raised
Exception information:
raised SYSTEM.ASSERTIONS.ASSERT_FAILURE : netlists.adb:596
Call stack traceback locations:
0x7f9caad254f1 0x563269302b6f 0x5632692fd22a 0x563269318f78 0x5632693192fc 0x563269471364 0x5632694713d8 0x56326946ae1d 0x5632694c7eff 0x563269410916 0x563269572a9b 0x5632691da949 0x7f9caa90d099 0x5632691d91a8 0xfffffffffffffffe
******************************************************************

Changing data_buffer to be a constant (e.g. constant data_buffer : data_array_t := (others => (others => '0'));) the problem does not happen.

ghdl / ghdl-yosys-plugin

Slicing vector from array results in SYSTEM.ASSERTIONS.ASSERT_FAILURE raised #83