Open dl3yc opened 3 years ago
I'm seeing similar issues with other IEEE logic e.g:
IIR_PREDEFINED_IEEE_STD_LOGIC_MISC_AND_REDUCE_SUV
Is this an unimplemented feature?
Yes, please create an issue with a testcase. In general that's rather quick to implement.
Description I get the following error when trying to synthesize using ghdl:
The code generates no errors during simulation.
Expected behaviour I expect the code to synthesize without errors.
How to reproduce? This demonstrates the problem:
Context Please, provide the following information:
version
tarball_url
GHDL 2.0.0-dev (1.0.0.r55.gf5e3ef10) [Dunoon edition]